ML6652 View Datasheet(PDF) - Micro Linear Corporation
Part Name
Description
Manufacturer
ML6652
Micro Linear Corporation
ML6652 Datasheet PDF : 28 Pages
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ML6652
CONTROL REGISTERS
Control Registers
Register 31 ADDR 11111 (bin) 1F (hex) All bits are R/W All bits default to 0
Bit
Name
Description
R/W
15 Power Down
Setting bit to 1 powers down all circuits and resets all
R/W
control logic. Register bits are not reset (except the management interface)
and new configuration data is not loaded
14 FOOUTOFF
Setting bit to 1 turns off the output stage of the Fiber Optic
R/W
driver leaving the output pins in a high impedance state.
Setting bit to 1 creates the exact same results as a 0 input on FOUTOFF#
13 TPOUTOFF
Setting bit to 1 turns off the output stage of the twisted pair
R/W
line driver leaving the output pins in a high impedance state. Setting bit
to 1 creates exact same result as 0 input on TPOUTOFF#
12 LPBKTOTP
Setting bit to 1 directs TPINP (pin 10) and TPINN (pin 11)
R/W
to loop back to TPOUTP (pin 1) and TPOUTN (pin 3). Including
the PLL in the 100Mbps signal path is controlled by <31.10>,
PLLLPBK#
11 LPBKTOFO
Setting bit to 1 directs FOINP (pin 33) and FOINN (pin 32)
R/W
to loop back to IOUT (pin 21) and IOUT# (pin 22). Including the
PLL in the 100Mbps signal path is controlled by <31.10> PLLLPBK#.
10
PLLLPBK#
Setting bit to 1 removes the clock/data recovery PLL from
R/W
the signal path during 100Mbps loop back modes
7-4
Reserved
3-0
Reserved
Default
0
0
0
0
0
0
Register 30 ADDR 11110 (bin) 1E (hex) All bits are R/W
Bit Name
15 ADVERTHD#
Description
Setting bit to 1 AND TRANSPARENT# <30.11> set to 1
causes Half Duplex capability to be advertised in FLP bursts
Setting bit to 0 AND TRANSPARENT# <30.11> set to 1
causes Half Duplex capability to not be advertised in FLP bursts
Setting TRANSPARENT# <30.11> to 0 causes ADVERTHD#
to be ignored
14
DSBLAN
Setting bit to 1 disables detection of FLNP and FLP bursts
13
RESET
12
LIW
Setting this bit to 1 causes all configuration pins to be read
and all register bits to be initialized 3 to 8µs after the bit is
returned to a 0. The bit is self clearing
Setting this bit to 1 enables the Link Integrity Warning function
11 TRANSPARENT#
10 ADVERTFD#
Setting bit to 1 enables NON-TRANSPARENT Mode of operation
Setting bit to 0 enables TRANSPARENT Mode of operation
Setting bit to 0 and TRANSPARENT# <30.11> set to 1
causes Full Duplex capability to be advertised in FLP bursts
Setting bits to 1 and TRANSPARENT# <30.11> set to 0
causes Full Duplex capability to not be advertised in FLP bursts
SettingTRANSPARENT# <30.11> to 0 causesADVERFTD#
to be ignored
R/W Default
R/W 0
R/W Set by
SPEED
(pin 27)
R/W 0
R/W Set by
AD4LIW
(pin 4)
R/W Set by
DUPLEX
(pin 25)
R/W Set by
DUPLEX
(pin 25)
21
January 2004
Final Datasheet
DS6652-F-02
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