Freescale Semiconductor, Inc.
Timing Diagrams
IN1, IN2, EN
(GIN)
OUTn
(GOUT)
tPZH*,
tPLH
(tTON)
50%
90%
10%
tPHL
(tTOFF)
VDDDETon
VDD
1.5 V
tVDDDET
3.5 V
50%
VDDDEToff
tVDDDET
90%
IM
0%
(<1.0 µA)
* The last state is “Z”.
Figure 2. tPLH, tPHL, and tPZH Timing
Figure 3. Low-Voltage Detection Timing
Table 1. Truth Table
INPUT
OUTPUT
EN
IN1
IN2
GIN
OUT1
OUT2
H
L
L
X
Z
Z
H
H
L
X
H
L
H
L
H
X
L
H
H
H
H
X
L
L
L
X
X
X
L
L
H
X
X
L
X
X
H
X
X
H
X
X
H = High.
L = Low.
Z = High impedance.
X = Don’t care.
The GIN terminal and EN terminal are pulled up to VDD with internal resistance.
GOUT
X
X
X
X
L
H
L
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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