MPC8540(2004) View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MPC8540
(Rev.:2004)

PowerQUICC III™ Integrated Host Processor Reference Manual

Freescale Semiconductor 

Contents

Paragraph

Number

Title

Page

Number

5.8

5.8.1

5.8.2

5.8.3

5.8.4

5.8.5

5.9

5.9.1

5.9.2

5.9.3

5.9.4

5.10

5.10.1

5.10.2

5.10.3

5.10.4

5.11

5.12

5.12.1

5.12.2

5.12.3

5.13

5.13.1

5.13.1.1

5.13.1.2

5.13.2

5.13.3

5.13.4

5.13.5

5.13.6

5.14

Interrupts and Exception Handling ................................................................................ 5-20

Exception Handling ................................................................................................... 5-20

Interrupt Classes ........................................................................................................ 5-21

Interrupt Types ........................................................................................................... 5-21

Upper Bound on Interrupt Latencies ......................................................................... 5-22

Interrupt Registers...................................................................................................... 5-22

Memory Management.................................................................................................... 5-24

Address Translation ................................................................................................... 5-26

MMU Assist Registers (MAS1–MAS4 and MAS6) ................................................. 5-27

Process ID Registers (PID0–PID2)............................................................................ 5-27

TLB Coherency.......................................................................................................... 5-27

Memory Coherency ....................................................................................................... 5-28

Atomic Update Memory References ......................................................................... 5-28

Memory Access Ordering.......................................................................................... 5-28

Cache Control Instructions ........................................................................................ 5-28

Programmable Page Characteristics .......................................................................... 5-29

Core Complex Bus (CCB) ............................................................................................. 5-29

Performance Monitoring................................................................................................ 5-29

Global Control Register ............................................................................................. 5-30

Performance Monitor Counter Registers ................................................................... 5-30

Local Control Registers ............................................................................................. 5-30

Legacy Support of PowerPC Architecture..................................................................... 5-31

Instruction Set Compatibility..................................................................................... 5-31

User Instruction Set ............................................................................................... 5-31

Supervisor Instruction Set...................................................................................... 5-31

Memory Subsystem ................................................................................................... 5-32

Exception Handling ................................................................................................... 5-32

Memory Management................................................................................................ 5-32

Reset........................................................................................................................... 5-32

Little-Endian Mode.................................................................................................... 5-33

PowerQUICC III Implementation Details ..................................................................... 5-33

6.1

6.1.1

6.2

6.2.1

6.3

Chapter 6

Core Register Summary

Overview.......................................................................................................................... 6-1

Register Set .................................................................................................................. 6-1

Register Model for 32-Bit Implementations .................................................................... 6-3

Special-Purpose Registers (SPRs) ............................................................................... 6-4

Registers for Computational Operations.......................................................................... 6-8

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

ix

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