MPC8544E View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MPC8544E

PowerQUICC III Integrated Processor Hardware Specifications

Freescale Semiconductor 

System Design Information

21.9.1 Termination of Unused Signals

If the JTAG interface and COP header will not be used, Freescale recommends the following connections:

• TRST should be tied to HRESET through a 0-kΩ isolation resistor so that it is asserted when the

system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during

the power-on reset flow. Freescale recommends that the COP header be designed into the system

as shown in Figure 69. If this is not possible, the isolation resistor will allow future access to TRST

in case a JTAG interface may need to be wired onto the system in future debug situations.

• No pull-up/pull-down is required for TDI, TMS, or TDO.

Figure 68 shows the COP connector physical pinout.

COP_TDO 1

2

COP_TDI 3

4

COP_RUN/STOP 5

6

COP_TCK 7

8

COP_TMS 9

10

COP_SRESET 11

12

COP_HRESET

13

KEY

No pin

COP_CHKSTP_OUT 15

16

NC

COP_TRST

COP_VDD_SENSE

COP_CHKSTP_IN

NC

NC

GND

Figure 68. COP Connector Physical Pinout

MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

111

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