MPC8544E View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MPC8544E

PowerQUICC III Integrated Processor Hardware Specifications

Freescale Semiconductor 

MPC8544E Overview

– Two key (K1, K2, K1) or three key (K1, K2, K3)

– ECB and CBC modes for both DES and 3DES

— AESU—Advanced Encryption Standard unit

– Implements the Rijndael symmetric key cipher

– ECB, CBC, CTR, and CCM modes

– 128-, 192-, and 256-bit key lengths

— AFEU—ARC four execution unit

– Implements a stream cipher compatible with the RC4 algorithm

– 40- to 128-bit programmable key

— MDEU—message digest execution unit

– SHA with 160- or 256-bit message digest

– MD5 with 128-bit message digest

– HMAC with either algorithm

— KEU—Kasumi execution unit

– Implements F8 algorithm for encryption and F9 algorithm for integrity checking

– Also supports A5/3 and GEA-3 algorithms

— RNG—random number generator

— XOR engine for parity checking in RAID storage applications

• Dual I2C controllers

— Two-wire interface

— Multiple master support

— Master or slave I2C mode support

— On-chip digital filtering rejects spikes on the bus

• Boot sequencer

— Optionally loads configuration data from serial ROM at reset via the I2C interface

— Can be used to initialize configuration registers and/or memory

— Supports extended I2C addressing mode

— Data integrity checked with preamble signature and CRC

• DUART

— Two 4-wire interfaces (SIN, SOUT, RTS, CTS)

— Programming model compatible with the original 16450 UART and the PC16550D

• Local bus controller (LBC)

— Multiplexed 32-bit address and data bus operating at up to 133 MHz

— Eight chip selects support eight external slaves

— Up to eight-beat burst transfers

— The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller.

— Two protocol engines available on a per chip select basis:

MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5

4

Freescale Semiconductor

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