MPC9774 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

MPC9774

3.3V/2.5V 1:14 LVCMOS PLL Clock Generator

Motorola => Freescale 

MPC9774

Using the MPC9774 in zero-delay applications

Nested clock trees are typical applications for the

MPC9774. Designs using the MPC9774 as LVCMOS PLL

fanout buffer with zero insertion delay will show significantly

lower clock skew than clock distributions developed from

CMOS fanout buffers. The external feedback of the

MPC9774 clock driver allows for its use as a zero delay

buffer. The PLL aligns the feedback clock output edge with

the clock input reference edge resulting a near zero delay

through the device (the propagation delay through the device

is virtually eliminated). The maximum insertion delay of the

device in zero-delay applications is measured between the

reference clock input and any output. This effective delay

consists of the static phase offset, I/O jitter (phase or

long-term jitter), feedback path delay and the

output-to-output skew error relative to the feedback output.

Calculation of part-to-part skew

The MPC9774 zero delay buffer supports applications

where critical clock signal timing can be maintained across

several devices. If the reference clock inputs of two or more

MPC9774 are connected together, the maximum overall

timing uncertainty from the common CCLK input to any

output is:

tSK(PP) = t(∅) + tSK(O) + tPD, LINE(FB) + tJIT(∅)
CF

This maximum timing uncertainty consist of 4

components: static phase offset, output skew, feedback

board trace delay and I/O (phase) jitter:

CCLKCommon

–t(∅)

tPD,LINE(FB)

QFBDevice 1

Any QDevice 1

tJIT(∅)

±tSK(O)

QFBDevice2

+t(∅)

tJIT(∅)

Any QDevice 2

±tSK(O)

Max. skew

tSK(PP)

Figure 5. MPC9774 max. device-to-device skew

Due to the statistical nature of I/O jitter a rms value (1 σ) is

specified. I/O jitter numbers for other confidence factors (CF)

can be derived from Table 12.

Table 12. MPC9774 Divider

CF

Probability of clock edge within the distribution

± 1s

0.68268948

± 2s

0.95449988

± 3s

0.99730007

± 4s

0.99993663

± 5s

0.99999943

± 6s

0.99999999

The feedback trace delay is determined by the board

layout and can be used to fine-tune the effective delay

through each device. In the following example calculation a

I/O jitter confidence factor of 99.7% (± 3σ) is assumed,

resulting in a worst case timing uncertainty from input to any

output of -495 ps to 495 ps2 relative to CCLK:

tSK(PP) =

[–300ps...300ps] + [–150ps...150ps] +

[(15ps @ –3)...(15ps @ 3)] + tPD, LINE(FB)

tSK(PP) = [–495ps...495ps] + tPD, LINE(FB)

Due to the frequency dependence of the I/O jitter, Figure 6

can be used for a more precise timing performance analysis.

TBD.

See MPC961C application section for an ex-

ample I/O jitter characteristic

Figure 6.

2. Final skew data pending specification

Driving Transmission Lines

The MPC9774 clock driver was designed to drive high

speed signals in a terminated transmission line environment.

To provide the optimum flexibility to the user the output

drivers were designed to exhibit the lowest impedance

possible. With an output impedance of less than 20Ω the

drivers can drive either parallel or series terminated

transmission lines. For more information on transmission

lines the reader is referred to Motorola application note

AN1091. In most high performance clock networks

point-to-point distribution of signals is the method of choice.

In a point-to-point scheme either series terminated or parallel

terminated transmission lines can be used. The parallel

technique terminates the signal at the end of the line with a

50Ω resistance to VCC ÷ 2.

This technique draws a fairly high level of DC current and

thus only a single terminated line can be driven by each

output of the MPC9774 clock driver. For the series

terminated case however there is no DC current draw, thus

the outputs can drive multiple series terminated lines.

Figure 7 “Single versus Dual Transmission Lines” illustrates

an output driving a single series terminated line versus two

series terminated lines in parallel. When taken to its extreme

the fanout of the MPC9774 clock driver is effectively doubled

due to its capability to drive multiple lines.

TIMING SOLUTIONS

9

MOTOROLA

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