MPC9855VF View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
MPC9855VF Datasheet PDF : 12 Pages
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Table 9. AC Characteristics (VDD = 3.3 V ± 5%, VDDOA = 3.3 V ± 5%, VDDOB = 3.3 V ± 5%, TA = –40°C to +85°C)(1) (2)
Symbol
Characteristics
Input and Output Timing Specification
fref
Input Reference Frequency (25 MHz input)
Input Reference Frequency (33 MHz input)
XTAL Input
Input Reference Frequency in PLL Bypass Mode(3)
fVCO
VCO Frequency Range(4)
fMCX
Output Frequency
Bank A output
Bank B output
Bank C output
frefPW
Reference Input Pulse Width
frefCcc
Input Frequency Accuracy
tr, tf
Output Rise/Fall Time
DC
Output Duty Cycle
PLL Specifications
BW
PLL Closed Loop Bandwidth(5)
tLOCK
Maximum PLL Lock Time
treset_ref
MR Hold Time on Power Up
treset_pulse MR Hold Time
Skew and Jitter Specifications
tsk(O)
Output-to-Output Skew (within a bank)
tsk(O)
Output-to-Output Skew (across banks A and B)
Min
15.87
15.87
50
2
80
47.5
45
10
10
tJIT(CC)
tJIT(PER)
tJIT(∅)
Cycle-to-cycle jitter
Period Jitter
I/O Phase Jitter
RMS (1 σ)
Typ
25
33
25
2000
50
50
50
100
150
80
150
80
15
15
Max
Unit
Condition
MHz
MHz
MHz
250
MHz PLL bypass
MHz
200
MHz PLL locked
200
MHz
500
MHz
ns
100
ppm
500
ns 20% to 80%
52.5
% 3.3 V operation
55
2.5 V operation
1
MHz
10
ms
ns
ns
ps
ps VDDOA = 3.3 V
VDDOB = 3.3 V
ps Bank A and B
Back C
ps Bank A and B
Back C
ps Bank A and B
Back C
1. AC characteristics are design targets and pending characterization.
2. AC characteristics apply for parallel output termination of 50 Ω to VTT.
3. In bypass mode, the MPC9855 divides the input reference clock.
4. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio:
fref = (fVCO ÷ M) ⋅ N.
5. –3 dB point of PLL transfer characteristics.
Pulse
Generator
Z = 50Ω
ZO = 50Ω
ZO = 50Ω
RT = 50Ω
DUT MPC9855
RT = 50Ω
VTT
VTT
Figure 4. MPC9855 AC Test Reference (LVCMOS Outputs)
MPC9855
8
Timing Solutions
Freescale Semiconductor
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