MSC5301B-02 View Datasheet(PDF) - Oki Electric Industry

Part Name

Description

Manufacturer

MSC5301B-02

LCD COMMON/SEGMENT DRIVER WITH RAM

Oki Electric Industry 

¡ Semiconductor

MSC5301B-02

• BLK (Pin 37)

This is an input pin to control the LCD panel display.

When a "H" level is input (or when this pin is open), the segment output pins S0 - S63 come to

the levels V2 - V3 and the LCD panel is turned off. In addition, during this period, the data read

from a display RAM is stopped but writing into the display RAM of address and segment data

inputted from the SI pin is available.

When this pin is changed from "H" level to "L", the frame synchronizing signal FRAM is output

within the 2 cycles of an internal clock ff, and it is synchronized at multi-chip. Then, the display

RAM address is set to "000". After 1/8 frame cycle from FRAM signal generation, the output

is applied from the "001" data of the display RAM address to the segment driver. Because the

display RAM contents are undefined at the time the power is turned on, keep this pin to "H"

level (or leave open) until writing data to the RAM is completed. A pull-up resistor (10kW -

60kW) and the Schmitt circuit are contained.

• POR (Pin 36)

This is a power-on-reset input pin. When a "H" level is input (or when this pin is open), the

common and segment outputs come to the static light-out state in no relation to the BLK pin

and the segment output pins S0 - S63 become V3 level and the common output pins C0 - C8

become V4 level.

When this pin is changed from "H" level to "L", the frame synchronizing signal FRAM is output

within the 2 cycles of an interval clock ff, and it is synchronized when multiple devices are

connected and is moreover dynamic-operated from the frame B . Then, the display RAM

address is set to "000". After 1/8 frame cycle from FRAM signal generation, the "001" data of

the display RAM address is output to the segment driver. However, because the BLK pin is

usually at "H" level when the power-on-reset is released, reading data from the display RAM

is stopped and light-out segment data is forcibly transferred to the segment output. A pull-up

resistor (10kW - 60kW) and the Schmitt circuit are contained.

• C0 (Pin 13) - C7 (Pin 27)

These are 8-output pins of the common driver which are used for LCD panel driving. The

outputs of 4 levels are obtained (VDSP and GND are select levels, and V1 and V4 are nonselect

levels).

• S0 (Pin 47) - S63 (Pin 11)

These are 64-output pins of segment driver which are used for LCD panel driving. The outputs

of 4 levels are obtained (VDSP and GND are select levels, which correspond to "1" of the display

RAM data, and V2 and V3 are nonselect levels, which correspond to "0" of the display RAM

data).

NOTES ON USE

Note the following when turning power on and off:

The LCD drivers of this IC require a high voltage. For this reason, if a high voltage is applied to

the LCD drivers with the logic power supply floating, excess current flows. This may damage

the IC. Be sure to carry out the following power-on and power-off sequences:

When turning power on:

First VCC ON, next VDSP, V4, V3, V2, V1 ON. Or both ON at the same time.

When turning power off:

First VDSP, V4, V3, V2, V1 OFF, next VCC OFF. Or both OFF at the same time.

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