MSM6895GS-BK View Datasheet(PDF) - Oki Electric Industry
Part Name
Description
Manufacturer
MSM6895GS-BK Datasheet PDF : 43 Pages
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¡ Semiconductor
MSM6895/6896
TEST, CK1536
External master clock inputs.
Since the MSM6895 and MSM6896 contain PLL internally, the external clock signal is eliminated.
But the device can operate with the external clock through these pins.
When these pins are not used, leave these pins open or at 0 V.
Mode
Internal PLL
External master clock
TEST pin
0V
Digital "1"
CK1536 pin
open or 0 V
Input the signal of 1536 kHz
When the external clock is used, the CK1536 signal is required to be synchronized in phase with
the CK8 signal.
CK64
CODEC PCM data input and output shift clock input.
When the continuous clock is set, the frequency is one of 64 kHz, 128 kHz, and 256 kHz. When
the burst clock is used, one of 192, 384, 768, 1536, and 2048 kHz is available. If the BCLOCK signal
is not applied, PLL is out of synchronization and goes into the self-running mode.
CK8
Synchronous signal input.
CODEC PCM data is sent out sequencially from MSB at the rising edge of the CK64 signal in
synchronization with the rise of the synchronous signal. PCM data should be entered from MSB
in synchronization with the rise of the synchronous signal. PCM data is shifted in at the falling
edge of the CK64 signal.
Since the CK8 signal is used for a trigger signal for PLL and for a clock signal to the tone generator,
if this signal is not applied, not only any tone can not be output, but also PLL goes out of
synchronization and goes into self-running mode. This signal has to be synchronous with the
CK64 signal and its frequency must be within 8 kHz ±50 ppm to ensure the CODEC AC
characteristics (mainly frequency characteristics).
LOSS
Signal output for controlling the external circuits.
When the howler tone of sounder is selected through processor control, the output is in a digital
"1".
Initially, this output is set to a digital "0".
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