MSM9810 View Datasheet(PDF) - Oki Electric Industry
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MSM9810 Datasheet PDF : 32 Pages
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¡ Semiconductor
MSM9810
9-6 FADR Command
The FADR command transfers data stored in the TMP register to the phrase address register of
the corresponding channel at the rise of the WR pulse.
For the phrase address, the user specification phrases have been set by an analysis tool, and the
playback system, sampling frequency and start and stop address of voice data have been
registered to the address management area.
When the phrase address is set and the START command is input, the LSI reads data of the
address management area, and starts voice synthesis.
Since the phrase address is set by D7-D0, a maximum of 256 phrases can be set. The edit function
can be used for phrase addresses, so not only one phrase but combinations with other phrases
are possible.
9-7 DADR Command
The DADR command transfers data stored in the TMP (1-7) register to the start and stop address
register of the corresponding channel at the rise of the WR pulse.
For the direct address, the playback system, sampling frequency, and start and stop address of
voice data is directly input from the microcomputer without using the address management
area.
Direct address playback system is available with channel 1 to 4, and not available with channel
5 to 8.
Since the phrases that can be set at a phrase address is a maximum of 256, if voice data exceeds
256 phrases, use this command. Data on the playback system, sampling frequency, and start and
stop address of voice data is displayed when an analysis tool is used.
Data on the playback system, sampling frequency, and start and stop address of voice data is
input to the TMP1 to TMP7 registers divided in 7 steps, unlike the data input of other commands.
Figure 9-4 shows the input method.
CMD(I)
CS(I)
WR(I)
D7 - D0(I)
Stores TMP1
Stores TMP3
Stores TMP5
Stores TMP7
register data
register data
register data
register data
Stores TMP2
register data
Stores TMP4
register data
Stores TMP6
register data
Executes command
Figure 9-4 DADR Input Timing
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