MSM9811GA View Datasheet(PDF) - Oki Electric Industry

Part Name

Description

Manufacturer

MSM9811GA

4-Channel Mixing OKI ADPCM Type Voice Synthesis LSI

Oki Electric Industry 

OKI Semiconductor

FEDL9811FULL-04

MSM9811

PIN DESCRIPTIONS

Pin

Symbol

40-47, 49-64 RA23-RA0

30, 31, 33-38 RD7-RD0

39

ROE

8

RCS

15

CMD

16

RD

18

WR

20

CS

14

SERIAL

28

D7/SD

27

D6/SI

26

D5/SO

Type

O

I

O

I

I

I

I

I

I

I/O

I/O

I/O

Description

Address pins for external memory. These pins become high impedance

when RCS pin is “H“.

Data pin for external memory. Pull-down resistors are internally

connected to these pins. These pull-down resistors become valid when

the RCS pin is “H”, and become invalid when the RCS pin is “L”.

Output enable pin for external memory. This pin becomes high

impedance when RCS pin is “H”.

When this pin is “L”, RA23 to RA0 and ROE pins output address data

and output enable signal.

When this pin is “H”, RA23 to RA0 and ROE pins become high

impedance.

Select pin for Command data or Subcommand data for CPU interface.

When this pin is “H”, subcommand input is selected.

When this pin is “L”, command input is selected. A pull-up resistor is

internally connected to this pin.

Read pin for CPU interface.

A pull-up resistor is internally connected to this pin.

Write pin for CPU interface.

A pull-up resistor is internally connected to this pin.

Chip select pin for CPU interface. When CS is “H”, WR signal is not

entered in this LSI. A pull-up resistor is internally connected to this pin.

CPU input interface select pin. When SERIAL is “H”, serial input

interface is selected.

When it is “L”, parallel input interface is selected.

Data bus pin for CPU interface when parallel input interface is selected.

When WR is “L”, this pin serves as data input pin.

When RD is “L”, this pin serves as channel status data output pin.

When serial input interface is selected, this pin serves as serial data

input pin.

Data bus pin for CPU interface when parallel input interface is selected.

When WR is “L”, this pin serves as data input pin.

When RD is “L”, this pin serves as channel status output pin.

When serial input interface is selected, this pin serves as serial clock

input pin.

Data bus pin for CPU interface when parallel input interface is selected.

When WR is “L”, this pin serves as data input pin.

When RD is “L”, this pin serves as channel status output pin.

When serial input interface is selected, this pin serves as channel status

serial output pin.

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