MSM9811GA View Datasheet(PDF) - Oki Electric Industry
Part Name
Description
Manufacturer
MSM9811GA Datasheet PDF : 44 Pages
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OKI Semiconductor
FEDL9811FULL-04
MSM9811
Pin
25
24
23
22
21
4
5
11
12
29
19
9
10
13
3
7, 48
6
1, 32
2
Symbol
D4/UD
D3/SR3
D2/SR2
D1/SR1
D0/SR0
LDAO
RDAO
XT
XT
RESET
NCR/BUSY
TEST1
TEST2
TEST3
TEST4
DVDD
AVDD
DGND
AGND
Type
I/O
I/O
O
O
I
O
I
I
I
—
—
—
—
Description
Data bus pin for CPU interface when parallel interface is selected.
When WR is “L”, this pin serves as data input pin.
When RD is “L”, this pin serves as channel status output pin.
When serial input interface is selected, fix this pin at GND level.
Data bus pin for CPU interface when parallel input interface is selected.
When WR is “L”, this pin serves as data input pin.
When RD is “L”, this pin serves as channel status output pin.
When serial input interface is selected, this pin serves as channel status
output pin.
Channels 4 thru 1 are output to SR3 thru SR0, respectively.
LEFT side D/A output pin.
RIGHT side D/A output pin.
Crystal or ceramic oscillator connection pin.
A feedback resistor of about 1MΩ is connected between XT and XT.
If necessary, enter external clocks into this pin.
Crystal or ceramic oscillator connection pin.
When external clocks are used, leave this pin open.
When this pin is “L” level, the LSI is initialized. At that time, oscillation
stops and D/A outputs go to GND level.
Channel status select pin.
When this pin is “H”, NCR signal is output. When it is “L”, BUSY signal is
output.
Pins for LSI testing. Apply “L” level to these pins.
Digital power supply pin. A bypass capacitor of 0.1 µF or more should
be connected between the DGND pin and the DVDD pin.
Analog power supply pin. A bypass capacitor of 0.1 µF or more should
be connected between the AGND pin and the AVDD pin.
Digital GND pin.
Analog GND pin.
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