MT16VDDF12864HG-202 View Datasheet(PDF) - Micron Technology
Part Name
Description
Manufacturer
MT16VDDF12864HG-202 Datasheet PDF : 31 Pages
| |||
Table 6: Burst Definition Table
BURST
LENGTH
STARTING
COLUMN
ADDRESS
ORDER OF ACCESSES WITHIN
A BURST
TYPE =
TYPE =
SEQUENTIAL INTERLEAVED
A0
2
0
0-1
0-1
1
1-0
1-0
A1 A0
00
0-1-2-3
0-1-2-3
4
01
1-2-3-0
1-0-3-2
10
2-3-0-1
2-3-0-1
11
3-0-1-2
3-2-1-0
A2 A1 A0
0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
8
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
NOTE:
1. For a burst length of two, A1-Ai select the two-data-ele-
ment block; A0 selects the first access within the block.
2. For a burst length of four, A2-Ai select the four-data-
element block; A0-A1 select the first access within the
block.
3. For a burst length of eight, A3-Ai select the eight-data-
element block; A0-A2 select the first access within the
block.
4. Whenever a boundary of the block is reached within a
given sequence above, the following access wraps
within the block.
5. i = 9 (512MB);
i = 9,11 (1GB)
Table 7: CAS Latency (CL) Table
SPEED
-335
-262
-26A
-265
-202
ALLOWABLE OPERATING
CLOCK FREQUENCY (MHZ)
CL = 2
75 £ f £ 133
75 £ f £ 133
75 £ f £ 133
75 £ f £ 100
75 £ f £ 100
CL = 2.5
75 £ f £ 167
75 £ f £ 133
75 £ f £ 133
75 £ f £ 133
75 £ f £ 125
512MB, 1GB (x64)
200-PIN DDR SODIMM
Figure 6: CAS Latency Diagram
CK#
CK
COMMAND
T0
READ
DQS
DQ
T1
NOP
CL = 2
T2 T2n T3 T3n
NOP
NOP
CK#
CK
COMMAND
T0
READ
DQS
DQ
T1
T2 T2n T3 T3n
NOP
NOP
NOP
CL = 2.5
Burst Length = 4 in the cases shown
Shown with nominal tAC, tDQSCK, and tDQSQ
TRANSITIONING DATA
DON T CARE
Operating Mode
The normal operating mode is selected by issuing a
MODE REGISTER SET command with bits A7–A12
each set to zero, and bits A0–A6 set to the desired val-
ues. A DLL reset is initiated by issuing a MODE REGIS-
TER SET command with bits A7 and A9–A12 each set
to zero, bit A8 set to one, and bits A0–A6 set to the
desired values. Although not required by the Micron
device, JEDEC specifications recommend when a
LOAD MODE REGISTER command is issued to reset
the DLL, it should always be followed by a LOAD
MODE REGISTER command to select normal operat-
ing mode.
All other combinations of values for A7–A12 are
reserved for future use and/or test modes. Test modes
and reserved states should not be used because
unknown operation or incompatibility with future ver-
sions may result.
Extended Mode Register
The extended mode register controls functions
beyond those controlled by the mode register; these
additional functions are DLL enable/disable and out-
put drive strength. These functions are controlled via
the bits shown in Figure 7, Extended Mode Register
Definition Diagram, on page 11. The extended mode
register is programmed via the LOAD MODE REGIS-
TER command to the mode register (with BA0 = 1 and
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
Share Link: 