MT41J128M View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT41J128M

DDR3 SDRAM

Micron Technology 

1Gb: x4, x8, x16 DDR3 SDRAM

RESET Operation

RESET Operation

The RESET signal (RESET#) is an asynchronous reset signal that triggers any time it

drops LOW, and there are no restrictions about when it can go LOW. After RESET# goes

LOW, it must remain LOW for 100ns. During this time, the outputs are disabled, ODT

(RTT) turns off (High-Z), and the DRAM resets itself. CKE should be driven LOW prior to

RESET# being driven HIGH. After RESET# goes HIGH, the DRAM must be re-initialized

as though a normal power-up was executed. All refresh counters on the DRAM are reset,

and data stored in the DRAM is assumed unknown after RESET# has gone LOW.

PDF: 09005aef826aa906

1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN

191

Micron Technology, Inc. reserves the right to change products or specifications without notice.

‹ 2006 Micron Technology, Inc. All rights reserved.

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