MT41J128M View Datasheet(PDF) - Micron Technology
Part Name
Description
Manufacturer
MT41J128M Datasheet PDF : 214 Pages
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1Gb: x4, x8, x16 DDR3 SDRAM
Features
DLL Disable Mode ..................................................................................................................................... 123
Input Clock Frequency Change ...................................................................................................................... 127
Write Leveling ............................................................................................................................................... 129
Write Leveling Procedure ........................................................................................................................... 131
Write Leveling Mode Exit Procedure ........................................................................................................... 133
Initialization ................................................................................................................................................. 134
Mode Registers .............................................................................................................................................. 136
Mode Register 0 (MR0) ................................................................................................................................... 137
Burst Length ............................................................................................................................................. 137
Burst Type ................................................................................................................................................. 138
DLL RESET ................................................................................................................................................ 139
Write Recovery .......................................................................................................................................... 139
Precharge Power-Down (Precharge PD) ...................................................................................................... 140
CAS Latency (CL) ....................................................................................................................................... 140
Mode Register 1 (MR1) ................................................................................................................................... 141
DLL Enable/DLL Disable ........................................................................................................................... 141
Output Drive Strength ............................................................................................................................... 142
OUTPUT ENABLE/DISABLE ...................................................................................................................... 142
TDQS Enable ............................................................................................................................................. 142
On-Die Termination .................................................................................................................................. 143
WRITE LEVELING ..................................................................................................................................... 143
POSTED CAS ADDITIVE Latency ................................................................................................................ 143
Mode Register 2 (MR2) ................................................................................................................................... 144
CAS Write Latency (CWL) ........................................................................................................................... 145
AUTO SELF REFRESH (ASR) ....................................................................................................................... 145
SELF REFRESH TEMPERATURE (SRT) ........................................................................................................ 146
SRT vs. ASR ............................................................................................................................................... 146
DYNAMIC ODT ......................................................................................................................................... 146
Mode Register 3 (MR3) ................................................................................................................................... 147
MULTIPURPOSE REGISTER (MPR) ............................................................................................................ 147
MPR Functional Description ...................................................................................................................... 148
MPR Register Address Definitions and Bursting Order ................................................................................. 149
MPR Read Predefined Pattern .................................................................................................................... 155
MODE REGISTER SET (MRS) Command ........................................................................................................ 155
ZQ CALIBRATION Operation ......................................................................................................................... 156
ACTIVATE Operation ..................................................................................................................................... 157
READ Operation ............................................................................................................................................ 159
WRITE Operation .......................................................................................................................................... 170
DQ Input Timing ....................................................................................................................................... 178
PRECHARGE Operation ................................................................................................................................. 180
SELF REFRESH Operation .............................................................................................................................. 180
Extended Temperature Usage ........................................................................................................................ 182
Power-Down Mode ........................................................................................................................................ 183
RESET Operation ........................................................................................................................................... 191
On-Die Termination (ODT) ............................................................................................................................ 193
Functional Representation of ODT ............................................................................................................. 193
Nominal ODT ............................................................................................................................................ 193
Dynamic ODT ............................................................................................................................................... 195
Dynamic ODT Special Use Case ................................................................................................................. 195
Functional Description .............................................................................................................................. 195
Synchronous ODT Mode ................................................................................................................................ 201
ODT Latency and Posted ODT .................................................................................................................... 201
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
4
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