MT41J128M View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT41J128M

DDR3 SDRAM

Micron Technology 

1Gb: x4, x8, x16 DDR3 SDRAM

Features

Table 51: DDR3-1066 Speed Bins ................................................................................................................... 74

Table 52: DDR3-1333 Speed Bins ................................................................................................................... 75

Table 53: DDR3-1600 Speed Bins ................................................................................................................... 76

Table 54: DDR3-1866 Speed Bins ................................................................................................................... 77

Table 55: DDR3-2133 Speed Bins ................................................................................................................... 78

Table 56: Electrical Characteristics and AC Operating Conditions .................................................................... 79

Table 57: Electrical Characteristics and AC Operating Conditions for Speed Extensions .................................... 89

Table 58: Command and Address Setup and Hold Values Referenced – AC/DC-Based ...................................... 99

Table 59: Derating Values for tIS/tIH – AC175/DC100-Based ........................................................................... 100

Table 60: Derating Values for tIS/tIH – AC150/DC100-Based ........................................................................... 100

Table 61: Derating Values for tIS/tIH – AC135/DC100-Based ........................................................................... 101

Table 62: Derating Values for tIS/tIH – AC125/DC100-Based ........................................................................... 101

Table 63: Minimum Required Time tVAC Above VIH(AC) or Below VIL(AC)for Valid Transition .............................. 102

Table 64: DDR3 Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based ......................... 107

Table 65: Derating Values for tDS/tDH – AC175/DC100-Based ........................................................................ 108

Table 66: Derating Values for tDS/tDH – AC150/DC100-Based ........................................................................ 108

Table 67: Derating Values for tDS/tDH – AC135/DC100-Based at 1V/ns ........................................................... 109

Table 68: Derating Values for tDS/tDH – AC135/DC100-Based at 2V/ns ........................................................... 110

Table 69: Required Minimum Time tVAC Above VIH(AC) (Below VIL(AC)) for Valid DQ Transition ......................... 111

Table 70: Truth Table – Command ................................................................................................................. 116

Table 71: Truth Table – CKE .......................................................................................................................... 118

Table 72: READ Command Summary ............................................................................................................ 120

Table 73: WRITE Command Summary .......................................................................................................... 120

Table 74: READ Electrical Characteristics, DLL Disable Mode ......................................................................... 126

Table 75: Write Leveling Matrix ..................................................................................................................... 130

Table 76: Burst Order .................................................................................................................................... 139

Table 77: MPR Functional Description of MR3 Bits ........................................................................................ 148

Table 78: MPR Readouts and Burst Order Bit Mapping ................................................................................... 149

Table 79: Self Refresh Temperature and Auto Self Refresh Description ............................................................ 182

Table 80: Self Refresh Mode Summary ........................................................................................................... 182

Table 81: Command to Power-Down Entry Parameters .................................................................................. 183

Table 82: Power-Down Modes ....................................................................................................................... 184

Table 83: Truth Table – ODT (Nominal) ......................................................................................................... 194

Table 84: ODT Parameters ............................................................................................................................ 194

Table 85: Write Leveling with Dynamic ODT Special Case .............................................................................. 195

Table 86: Dynamic ODT Specific Parameters ................................................................................................. 196

Table 87: Mode Registers for RTT,nom ............................................................................................................. 196

Table 88: Mode Registers for RTT(WR) ............................................................................................................. 197

Table 89: Timing Diagrams for Dynamic ODT ................................................................................................ 197

Table 90: Synchronous ODT Parameters ........................................................................................................ 202

Table 91: Asynchronous ODT Timing Parameters for All Speed Bins ............................................................... 207

Table 92: ODT Parameters for Power-Down (DLL Off ) Entry and Exit Transition Period ................................... 209

PDF: 09005aef826aa906

1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN

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