MT48LC1M16A1 View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT48LC1M16A1

SYNCHRONOUS DRAM

Micron Technology 

GENERAL DESCRIPTION

The 16Mb SDRAM is a high-speed CMOS, dynamic

random-access memory containing 16,777,216 bits. It is

internally configured as a dual 512K x 16 DRAM with a

synchronous interface (all signals are registered on the

positive edge of the clock signal, CLK). Each of the 512K x

16-bit banks is organized as 2,048 rows by 256 columns by

16 bits. Read and write accesses to the SDRAM are burst

oriented; accesses start at a selected location and continue

for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an

ACTIVE command, which is then followed by a READ or

WRITE command. The address bits registered coincident

with the ACTIVE command are used to select the bank and

row to be accessed (BA selects the bank, A0-A10 select the

row). The address bits registered coincident with the READ

or WRITE command are used to select the starting column

location for the burst access.

The SDRAM provides for programmable READ or

WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page,

with a burst terminate option. An AUTO PRECHARGE

function may be enabled to provide a self-timed row

16Mb: x16

IT SDRAM

precharge that is initiated at the end of the burst sequence.

The 1 Meg x 16 SDRAM uses an internal pipelined

architecture to achieve high-speed operation. This archi-

tecture is compatible with the 2n rule of prefetch architec-

tures, but it also allows the column address to be changed

on every clock cycle to achieve a high-speed, fully random

access. Precharging one bank while accessing the alter-

nate bank will hide the PRECHARGE cycles and provide

seamless, high-speed, random-access operation.

The 1 Meg x 16 SDRAM is designed to operate in 3.3V,

low-power memory systems. An auto refresh mode is

provided, along with a power-saving, power-down mode.

All inputs and outputs are LVTTL-compatible.

SDRAMs offer substantial advances in DRAM operat-

ing performance, including the ability to synchronously

burst data at a high data rate with automatic column-

address generation, the ability to interleave between inter-

nal banks in order to hide precharge time, and the capability

to randomly change column addresses on each clock cycle

during a burst access.

16Mb: x16 IT SDRAM

16MSDRAMx16IT.p65 – Rev. 5/99

2

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©1999, Micron Technology, Inc.

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