MT48LC1M16A1TG-6S View Datasheet(PDF) - Micron Technology
Part Name
Description
Manufacturer
MT48LC1M16A1TG-6S Datasheet PDF : 51 Pages
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READ – WITH AUTO PRECHARGE 1
T0
CLK
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
T1
tCK
NOP
DQM3
A0-A9
tAS tAH
ROW
T2
tCL
tCH
READ
tCMS tCMH
COLUMN m
(A0 - A7)2
T3
NOP
tAS tAH
A10
ROW
tAS tAH
BA
BANK
ENABLE AUTO PRECHARGE
BANK
DQ
tRCD
tRAS
tRC
tAC
tLZ
CAS Latency
T4
T5
T6
NOP
NOP
NOP
tAC
tOH
DOUT m
tAC
tOH
DOUT m + 1
tAC
tOH
DOUT m + 2
tRP
16Mb: x16
IT SDRAM
T7
T8
NOP
ACTIVE
ROW
ROW
tOH
DOUTm + 3
tHZ
BANK
TIMING PARAMETERS
SYMBOL*
tAC (3)
tAC (2)
tAC (1)
tAH
tAS
tCH
tCL
tCK (3)
tCK (2)
tCK (1)
tCKH
tCKS
-6
MIN MAX
5.5
8
18
1
2
2.5
2.5
6
8
20
1
2
-7
MIN MAX
5.5
8.5
22
1
2
2.75
2.75
7
10
25
1
2
-8A
MIN MAX
6
9
22
1
2
3
3
8
13
25
1
2
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DON’T CARE
UNDEFINED
SYMBOL*
tCMH
tCMS
tHZ (3)
tHZ (2)
tHZ (1)
tLZ
tOH
tRAS
tRC
tRCD
tRP
-6
MIN MAX
1
2
5.5
6
18
1
1.5
42 120,000
60
18
18
-7
MIN MAX
1
2
5.5
8.5
22
1
1.5
42 120,000
70
20
21
-8A
MIN MAX UNITS
1
ns
2
ns
6
ns
9
ns
22
ns
1
ns
1.5
ns
48 120,000 ns
80
ns
24
ns
24
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. A8 and A9 = “Don’t Care.”
3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
41
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
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