MT48LC2M32B2 View Datasheet(PDF) - Micron Technology
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Description
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MT48LC2M32B2 Datasheet PDF : 53 Pages
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three; data element n + 3 is either the last of a burst of
four or the last desired of a longer burst. This 64Mb
SDRAM uses a pipelined architecture and therefore
does not require the 2n rule associated with a prefetch
architecture. A READ command can be initiated on any
64Mb: x32
SDRAM
clock cycle following a previous READ command. Full-
speed random read accesses can be performed to the
same bank, as shown in Figure 8, or each subsequent
READ may be performed to a different bank.
T0
CLK
Figure 7
Consecutive READ Bursts
T1
T2
T3
T4
T5
COMMAND
READ
NOP
NOP
ADDRESS
BANK,
COL n
NOP
READ
NOP
X = 0 cycles
BANK,
COL b
DQ
DOUT
n
CAS Latency = 1
DOUT
n+1
DOUT
n+2
DOUT
n+3
DOUT
b
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
NOP
NOP
NOP
READ
NOP
NOP
ADDRESS
BANK,
COL n
X = 1 cycle
BANK,
COL b
DQ
CAS Latency = 2
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
DOUT
b
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
ADDRESS
BANK,
COL n
BANK,
COL b
X = 2 cycles
DQ
DOUT
n
DOUT
n+1
DOUT
n+2
CAS Latency = 3
NOTE: Each READ command may be to either bank. DQM is LOW.
DOUT
n+3
DOUT
b
DON’T CARE
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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