MT48LC16M8A2TG-7ELIT View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT48LC16M8A2TG-7ELIT

SYNCHRONOUS DRAM

Micron Technology 

CAS Latency

The CAS latency is the delay, in clock cycles, between

the registration of a READ command and the availability

of the first piece of output data. The latency can be set to

two or three clocks.

If a READ command is registered at clock edge n, and

the latency is m clocks, the data will be available by clock

edge n + m. The DQs will start driving as a result of the

clock edge one cycle earlier (n + m - 1), and provided that

the relevant access times are met, the data will be valid by

clock edge n + m. For example, assuming that the clock

cycle time is such that all relevant access times are met,

if a READ command is registered at T0 and the latency is

programmed to two clocks, the DQs will start driving

after T1 and the data will be valid by T2, as shown in

Figure 2. Table 2 below indicates the operating frequen-

cies at which each CAS latency setting can be used.

Reserved states should not be used as unknown op-

eration or incompatibility with future versions

may result.

T0

T1

T2

T3

CLK

COMMAND

DQ

READ

NOP

tLZ

tAC

CAS Latency = 2

NOP

tOH

DOUT

128Mb: x4, x8, x16

SDRAM

Operating Mode

The normal operating mode is selected by setting M7

and M8 to zero; the other combinations of values for M7

and M8 are reserved for future use and/or test modes.

The programmed burst length applies to both READ and

WRITE bursts.

Test modes and reserved states should not be used

because unknown operation or incompatibility with fu-

ture versions may result.

Write Burst Mode

When M9 = 0, the burst length programmed via

M0-M2 applies to both READ and WRITE bursts; when

M9 = 1, the programmed burst length applies to

READ bursts, but write accesses are single-location

(nonburst) accesses.

SPEED

-7E

-75

-8E

Table 2

CAS Latency

ALLOWABLE OPERATING

FREQUENCY (MHz)

CAS

LATENCY = 2

CAS

LATENCY = 3

≤ 133

≤ 100

≤ 100

≤ 143

≤ 133

≤ 125

CLK

COMMAND

T0

READ

DQ

T1

T2

NOP

NOP

tLZ

tAC

CAS Latency = 3

Figure 2

CAS Latency

T3

T4

NOP

tOH

DOUT

DON’T CARE

UNDEFINED

128Mb: x4, x8, x16 SDRAM

128MSDRAM_E.p65 – Rev. E; Pub. 1/02

11

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2001, Micron Technology, Inc.

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