MT48LC8M32B2TG-6 View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT48LC8M32B2TG-6

SYNCHRONOUS DRAM

Micron Technology 

T0

CLK

Figure 8

Random READ Accesses

T1

T2

T3

T4

PRELIMINARY

256Mb: x32

SDRAM

COMMAND

READ

READ

READ

READ

NOP

ADDRESS

BANK,

COL n

BANK,

COL a

BANK,

COL x

BANK,

COL m

DQ

DOUT

n

CAS Latency = 1

DOUT

a

DOUT

x

DOUT

m

T0

T1

T2

T3

CLK

T4

T5

COMMAND

READ

READ

READ

READ

NOP

NOP

ADDRESS

BANK,

COL n

BANK,

COL a

BANK,

COL x

BANK,

COL m

DQ

DOUT

n

DOUT

a

CAS Latency = 2

DOUT

x

DOUT

m

T0

T1

T2

T3

T4

T5

T6

CLK

COMMAND

READ

READ

READ

READ

NOP

NOP

NOP

ADDRESS

BANK,

COL n

BANK,

COL a

BANK,

COL x

BANK,

COL m

DQ

DOUT

n

DOUT

a

CAS Latency = 3

NOTE: Each READ command may be to either bank. DQM is LOW.

DOUT

x

DOUT

m

DON’T CARE

09005aef80cd8e48

256MbSDRAMx32.p65 – Rev. B; Pub. 03/04

18

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2003 Micron Technology, Inc.

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