MT8926 View Datasheet(PDF) - Mitel Networks
Part Name
Description
Manufacturer
MT8926 Datasheet PDF : 26 Pages
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MT8926
Pin Description (Continued)
Pin #
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Name
Description
C2i 2.048 MHz Clock Input. This input accepts a 2.048 MHz clock signal, which is used to
clock ST-BUS control and data streams into and out of the PMAC. See Figures 13 and
14 for timing information.
VSS System Ground.
VDD Supply Voltage Input (+5 V).
RESET RESET Input. Must be high for normal operation. When low, the functions of the
MT8926 will be suspended.
FDLi
Facility Data Link Input. This input accepts a 4 kbit/sec. facility data link transmit
signal, which is routed back out transparently on FDLo if message-oriented signal
transmission is enabled (i.e., PMAC Control Word bit 0, FDLEn, is low). This signal is
not clocked into the PMAC. If bit-oriented messaging is enabled (FDLEn high), data on
this input will not be routed to FDLo (see pin 18, FDLo, below).
FDLo
1SEC
Facility Data Link Output. When bit-oriented messaging is enabled (i.e., PMAC
Control Word bit 0, FDLEn, is high), data in the Transmit BOM register will be appended
to a 1111 1111 (FF) flag and clocked out of the device at this output. The output timing
for this signal is shown in Figure 18. When bit-oriented messaging is disabled (FDLEn
low), data received at the FDLi pin is routed back out transparently on this pin (it is not
re-timed). See Figure 19 for timing information.
1 Second Output. A one second timing signal derived from the ST-BUS F0i signal is
output on this pin. The output is low for 0.5 seconds and high for 0.5 seconds. It can be
used as an interrupt source to generate T1.403 message-oriented performance reports.
See Figure 16 for timing information.
IRQ Interrupt Request Output. An open drain output that is to be externally connected to
VDD through a pull-up resistor. The PMAC will pull this pin low to assert an interrupt
request. Interrupting events and their groupings are described in Tables 16 and 17. IRQ
is released by making bit 1 (Interrupt Acknowledge - INTA) of the PMAC Control Word
low. Once INTA is set, all interrupting signals of a particular group must be inactive
before the next interrupt of that group can assert IRQ. See Figure 17 for functional
timing information.
IC Internal Connection. Must be left open for normal operation.
VSS
IC
DSTo
System Ground.
Internal Connection. Must be left open for normal operation.
Data ST-BUS Output. A 2.048 MBit/sec. serial output stream, which contains the 24
PCM or data channels to be transmitted on the T1 trunk. This data stream is
multiplexed from either input DSTi0 (Normal Mode) or input DSTi1 (Payload Loopback
Mode). The selection of either the Normal or Payload Loopback mode is made through
the Loopback Control Word. This output should be connected to DSTi of the MT8976/
77. When the loopback control word is set for line loopback code generation, the 24
PCM channels will contain the line loopback activate or deactivate code stream. See
Figure 14 for timing information.
DSTi0 Data ST-BUS Input 0. A 2.048 MBit/sec. serial input stream, which contains the 24
PCM or data channels to be transmitted on the T1 trunk in Normal Mode. This input
should be connected to the system side output stream.
DSTi1 Data ST-BUS Input 1. A 2.048 MBit/sec. serial input stream, which contains the 24
PCM or data channels to be transmitted on the T1 trunk in Payload Loopback Mode.
This input should be connected to DSTo of the MT8976/77.
IC Internal Connection. Must be tied to VSS for normal operation.
VDD Supply Voltage Input (+5 V).
4-5
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