LRS1805A View Datasheet(PDF) - Sharp Electronics
Part Name
Description
Manufacturer
LRS1805A Datasheet PDF : 57 Pages
| |||
sharp
LRS1805A
5
3. Truth Table
3.1 Bus Operation(1)
Flash
Smart
combo Notes F-CE F-RST F-OE F-WE S-CE1 S-CE2 S-OE S-WE S-LB S-UB DQ0 to DQ15
RAM
Read
Output
Disable
Write
Read
Output
Disable
Write
3,5
Standby 5
L
2,3,4,5
3,5
Sleep
5
L
Read
2,3,4,5
5,6
L
H
H
HHXX
H
L
L
H
H
XLXX
H
L
LH
(7)
X
High - Z
DIN
(7)
X
High - Z
DIN
(8)
Standby
Output
Disable
5,6
H
H
XHHH
XXLH
HHXX
High - Z
Write
5,6
XL
(8)
Read
5,6
LH
(8)
Reset Power Output
Down
Disable
5,6
X
L
XHHH
XXLH
HHXX
High - Z
Write
5,6
XL
(8)
Standby
5
H
H
Reset Power Standby
Down
5,6
X
L
XXHHXX
X
High - Z
Standby
5
H
H
Reset Power Sleep
Down
5,6 X
XXXLXX
L
X
High - Z
Notes:
1. L = VIL, H = VIH, X = H or L, High-Z = High impedance. Refer to the DC Characteristics.
2. Command writes involving block erase (page buffer) program are reliably executed when F-VPP = VPPH1/2 and F-VCC
= 2.7V to 3.3V.
Command writes involving full chip erase is reliably executed when F-VPP = VPPH1 and F-VCC = 2.7V to 3.3V.
Block erase, full chip erase, (page buffer) program with F-VPP < VPPH1/2 (Min.) produce spurious results and should not
be attempted.
3. Never hold F-OE low and F-WE low at the same timing.
4. Refer Section 5. Command Definitions for Flash Memory valid DIN during a write operation.
5. F-WP set to VIL or VIH.
6. Electricity consumption of Flash Memory is lowest when F-RST = GND ±0.2V.
7. Flash Read Mode
Mode
Read Array
Read Identifier Codes
Read Query
Address
X
See 5.2
DQ0 to DQ15
DOUT
See 5.2
Refer to the Appendix Refer to the Appendix
8. S-UB, S-LB Control Mode
S-LB S-UB DQ0 to DQ7 DQ8 to DQ15
L
L
DOUT/DIN
DOUT/DIN
L
H
DOUT/DIN
High - Z
HL
High - Z
DOUT/DIN
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