HYB39S64800ATL View Datasheet(PDF) - Infineon Technologies

Part Name

Description

Manufacturer

HYB39S64800ATL

64Mbit Synchronous DRAM

Infineon Technologies 

64 MBit Synchronous DRAM

HYB39S64400/800/160AT(L)

64MBit Synchronous DRAM

• High Performance:

-8 -8B -10 Units

fCKmax. 125 100 100 MHz

tCK3

8

10

10

ns

tAC3

6

6

7

ns

tCK2

10

12

15

ns

tAC2

6

7

8

ns

• Fully Synchronous to Positive Clock Edge

• 0 to 70 °C operating temperature

• Four Banks controlled by BA0 & BA1

• Programmable CAS Latency: 2 & 3

• Programmable Wrap Sequence: Sequential

or Interleave

• Programmable Burst Length: 1, 2, 4, 8

• full page (optional) for sequential wrap

around

• Multiple Burst Read with Single Write

Operation

• Automatic and Controlled Precharge

Command

• Data Mask for Read / Write control (x4, x8)

• Data Mask for byte control (x16)

• Auto Refresh (CBR) and Self Refresh

• Suspend Mode and Power Down Mode

• 4096 refresh cycles / 64 ms

• Random Column Address every CLK

( 1-N Rule)

• Single 3.3V +/- 0.3V Power Supply

• LVTTL Interface version

• Plastic Packages:

P-TSOPII-54 400mil width (x4, x8, x16)

• -8 version for PC100 2-2-2 applications

-8B version for PC100 3-2-3 applications

The HYB39S64400/800/160AT are four bank Synchronous DRAM’s organized as 4 banks x 4MBit

x4, 4 banks x 2MBit x8 and 4 banks x 1Mbit x16 respectively. These synchronous devices achieve

high speed data transfer rates by employing a chip architecture that prefetches multiple bits and

then synchronizes the output data to a system clock. The chip is fabricated with SIEMENS’

advanced quarter micron 64MBit DRAM process technology.

The device is designed to comply with all JEDEC standards set for synchronous DRAM products,

both electrically and mechanically. All of the control, address, data input and output circuits are

synchronized with the positive edge of an externally supplied clock.

Operating the four memory banks in an interleave fashion allows random access operation to occur

at higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible

depending on burst length, CAS latency and speed grade of the device.

Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a

single 3.3V +/- 0.3V power supply and are available in TSOPII packages.

The -8 version of this product is best suited for use on a 100 Mhz bus for both CAS latencies 2 & 3.

Semiconductor Group

1

10.98

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