MX844 View Datasheet(PDF) - IXYS CORPORATION
Part Name
Description
Manufacturer
MX844 Datasheet PDF : 21 Pages
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MX844
IXYS
Analog/Digital Converter
Selection of the input channel and the full scale range is accomplished by writing 5 bits in the control
register. An additional 3 bits in the control register in combination with the M1 pin setup the internal clock
dividers. The ADC is a bipolar-input dual slope type with clock period tAD equal to a multiple of the clock
period at pin X1 (tClock). The ADC conversion time consists of 1024 * tAD of auto-zero, 1024 * tAD of
input integration, and 2048 * tAD of reference integration. The result of the analog to digital conversion
can be read using the serial I/O port and is also transmitted on pin AOUT in an asynchronous serial
format. The DRDY pin transitions low at the end of the reference integration period to indicate that data is
stable and may be read through the synchronous serial I/O. The data becomes not valid when DRDY
returns high. The status of DRDY is also available in bit 7 of the ADC_1 register.
The SYNC pin is connected to GND to enable free-running ADC conversions. Alternatively, if SYNC
transitions high, the ADC is immediately driven to the start of the auto-zero time. When SYNC is returned
to a logic low, the next rising edge at pin X2 will start the ADC timing.
The input channel and full scale range may be changed in between ADC conversions, however it is
recommended that such commands be written into the MX844 as soon as possible after pin DRDY
transitions low. This allows the maximum settling time prior to the next ADC conversion.
ADC clock # 0
1023 1024
2047 2048
4095 0
1023 1024
auto-zero
input integrate
reference integrate
next auto-zero
2047 2048
SYNC
DRDY (active low)
CMP (active low)
AOUT
6 data bits
DRDY and CMP cleared if ADC_2 register is read
6 data bits
CMP is the digital compare output that is described later. AOUT is the asynchronous serial output of the
ADC.
The ADC output code is offset-binary. An example of the coding is shown here for the +/-50mV range and
the corresponding unipolar range of 0 to 100mV:
Bipolar input
50mV
0 + 1/2 LSB
0 - 1/2 LSB
-50mV
Unipolar input
100mV
50mV + 1/2 LSB
50mV - 1/2 LSB
0
Binary Output (D11:D0)
111111111111
100000000000
011111111111
000000000000
Hexadecimal
FFF
800
7FF
000
Two external components, Rin and Cint, should be chosen such that the value of Cint in pF is 4 to 7 * tAD
and the time constant of Rint * Cint is 300 to 450 * tAD. The value of Rint should be between 47K and
220K ohm. For example, for t(AD) = 1.6 uS, a set of suitable values would be 56K ohm and 10nF (RC =
560uS, ratio = 350). The value of the auto-zero capacitor Caz is typically equal to Cint.
VTRIM is either a no-connect pin or can be used to fine
trim the ADC full scale by +/- 1%. The following circuit
is recommended if fine trimming is desired:
VCC
20K
1K
VTRIM
GND
MX844
Drawing No. 084423
5
08/25/06
www.claremicronix.com
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