NCP382 View Datasheet(PDF) - ON Semiconductor

Part Name

Description

Manufacturer

NCP382

Fixed Current-Limiting Power-Distribution Switches

ON Semiconductor 

NCP382

Enable Input

Enable pin must be driven by a logic signal (CMOS or

TTL compatible) or connected to the GND or VIN. A logic

low on ENX or high on ENX turns−on the device. A logic

high on ENX or low on ENX turns off device and reduces

the current consumption down to IINOFF.

Blocking Control

The blocking control circuitry switches the bulk of the

power MOS. When the part is off, the body diode limits the

leakage current IREV from OUTX to IN. In this mode, anode

of the body diode is connected to IN pin and cathode is

connected to OUTX pin. In operating condition, anode of

the body diode is connected to OUTX pin and cathode is

connected to IN pin preventing the discharge of the power

supply.

APPLICATION INFORMATION

Power Dissipation

The junction temperature of the device depends on

different contributing factors such as board layout, ambient

temperature, device environment, etc... Yet, the main

contributor in term of junction temperature is the power

dissipation of the power MOSFET. Assuming this, the

power dissipation and the junction temperature in normal

mode can be calculated with the following equations:

ǒ Ǔ PD + RDS(on)

ǒIOUT1Ǔ2 ) ǒIOUT2Ǔ2

(eq. 2)

PD

RDS(on)

IOUTx

TJ

RqJA

TA

= Power dissipation (W)

= Power MOSFET on resistance (W)

= Output current in channel X (A)

TJ + PD RqJA ) TA

(eq. 3)

= Junction temperature (°C)

= Package thermal resistance (°C/W)

= Ambient temperature (°C)

Power dissipation in regulation mode can be calculated by

taking into account the drop VIN −VOUTX link to the load by

the following relation:

ǒ Ǔ ǒ Ǔ ǒ Ǔ PD + VIN * RLOAD1 IOCP ) VIN * RLOAD2 IOCP

IOCP

(eq. 4)

PD

VIN

RLOADX

IOCP

= Power dissipation (W)

= Input Voltage (V)

= Load Resistance on channel X (W)

= Output regulated current (A)

PCB Recommendations

The NCP382 integrates two PMOS FET rated up to 2 A,

and the PCB design rules must be respected to properly

evacuate the heat out of the silicon. The DFN8 PAD1 must

be connected to ground plane to increase the heat transfer if

necessary. Of course, in any case, this pad must not connect

to any other potential. By increasing PCB area, the RqJA of

the package can be decreased, allowing higher current.

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