NJU26188 View Datasheet(PDF) - Japan Radio Corporation
Part Name
Description
Manufacturer
NJU26188 Datasheet PDF : 17 Pages
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NJU26100 Series
Table 5-2 4-Wire Serial Interface Timing Parameters (VDDO=VDDC=VDDR=2.5V, VSSO=VSSC=VSSR=0V, Ta=25°C)
Parameter
Symbol
Timelines
Min. Typ. Max. Units
Input Data Rising Time
Input Data Falling Time
Serial Clock Rising Time
Serial Clock Falling Time
Serial Strobe Rising Time
Serial Strobe Falling Time
Serial Clock High Duration
Serial Clock Low Duration
Serial Clock Period
Serial Strobe Setup Time
Serial Strobe Hold Time
Serial Strobe Low Duration
Serial Strobe High Duration
Input Data Setup Time
Input Data Hold Time
Output Data Delay
(From SSb)
tMSDr
tMSDf
tMSCr
tMSCf
tMSSr
tMSSf
tMSCa
tMSCn
tMSCc
tMSSs
tMSSh
tMSSa
tMSSn
tMSDis
tMSDih
a-b
-
-
100
ns
a-b
-
-
100
ns
d-e
-
-
100
ns
f-g
-
-
100
ns
p-q
-
-
100
ns
m-n
-
-
100
ns
e-f
50
-
-
ns
g-h
50
-
-
ns
e-i
250
-
ns
n-e
100
-
ns
j-q
30
-
ns
n-p
-
1.0
-
µs
q-r
40
-
ns
b-e
20
-
ns
e-c
20
-
ns
tMSDos
n-o,CL=25pF
-
-
50
ns
Output Data Delay
(From SCK)
tMSDo
g-k(data-6),
CL=25pF
-
-
50
ns
Output Data Hold Time
Output Data Turn off Time (Hi-Z)
tMSDoh
g-k(data-7)
0
tMSDov
q-l
-
-
-
ns
-
40
ns
ab
c
SDIN
7
6
5
d ef g h i
SCK
1
0
j
SDOUT Hi-Z
7
6
5
mn o
k
SSb
MSB
1
0
Note (3) Hi-Z
l
LSB
pqr
Fig. 5-1 4-Wire Serial Interface Timing
Note : *1 When the data-clock is less than 8 clocks, the input data is shifted to LSB side and is sent to the DSP
core at the transition of SSb=”High”.
*2 When the data-clock is more than 8 clocks, the last 8 bit data becomes valid.
*3 After sending LSB data, SDOUT transmits the MSB data which is received via SDIN until SSb becomes
“High”.
*4 SDOUT is Hi-Z in case of SSb = “High”. SDOUT is CMOS output in case of SSb = “Low”.
SDOUT needs a pull-up resistor to prevent SDOUT from becoming floating level.
- 14 -
Ver.2005-02-24
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