NJU26100 View Datasheet(PDF) - Japan Radio Corporation

Part Name

Description

Manufacturer

NJU26100

NJU26100 Series Hardware Specification

Japan Radio Corporation  

NJU26100 Series

2. Clock and Reset

The NJU26100 Series XI pin requires the system clock that should be related to the sample frequency Fs. The

XI/XO pins can generate the system clock by connecting the crystal oscillator or the ceramic resonator.

When the external oscillator is connected to XI/XO pins, check the voltage level of the pins. Because the

maximum input voltage level of XI pin is deferent from the other input or bi-directional pins. The maximum

voltage-level of XI pin equals to VDD.

To initialize the NJU26100 Series, RESETb pin should be set Low level during some period. After some period of

Low level, RESETb pin should be High level. This procedure starts the initialization of the NJU26100 Series.

To select I2C bus or 4-Wire serial bus, some level should be supplied to GPIO0 pin (SEL1 pin). When GPIO0 pin

(SEL1 pin)=”Low”, I2C bus is selected. When GPIO0 pin (SEL1 pin)=”High”, 4-Wire serial bus is selected. The level

of GPIO0 pin (SEL1 pin) is checked by the NJU26100 Series in 1 m sec after RESETb pin level goes to “High”.

After the power supply and the oscillation of the NJU26100 Series becomes stable, RESETb pin should be kept

Low-level more than tRESETb period.

VDD

XI

RESETb

OSC unstable

OSC stable

tRESETb

Fig. 2- 1 Reset Timing

Table 2- 1 Reset Time

Symbol

Time

tRESETb

≥1µs

Notice :

Please consult with manufacture of crystal oscillator / ceramic resonator enough in use of these parts.

NJRC would not take the responsibility on the external parts of clock generating.

Ver.2005-02-24

-5-

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