NM24C65U View Datasheet(PDF) - Fairchild Semiconductor

Part Name

Description

Manufacturer

NM24C65U

64K-Bit Serial EEPROM with Write Protect 2-Wire Bus Interface

Fairchild Semiconductor 

Write Cycle Timing

ACKNOWLEDGE

Acknowledge is a hardware convention used to indicate success-

ful data transfers. The transmitting device, either master or slave,

will release the bus after transmitting eight bits. During the ninth

clock cycle the receiver will pull the SDA line LOW to acknowledge

that it received the eight bits of data. Refer to Figure 4.

The NM24C65Uxxx device will always respond with an acknowl-

edge after recognition of a start condition and its slave address. If

Write Cycle Timing (Figure 1)

both the device and a WRITE operation have been selected, the

NM24C65Uxxx will respond with an acknowledge after the receipt

of each subsequent eight bit word.

In the READ mode the NM24C65Uxxx slave will transmit eight bits

of data, release the SDA line and monitor the line for an acknowl-

edge. If an acknowledge is detected and no stop condition is

generated by the master, the slave will continue to transmit data.

If an acknowledge is not detected, the slave will terminate further

data transmissions and await the stop condition to return to the

standby power mode.

SCL

SDA

8th BIT

WORD n

ACK

Data Validity (Figure 2)

tWR

STOP

START

CONDITION

CONDITION

DS800012-4

SCL

SDA

DATA STABLE DATA

CHANGE

Definition of Start and Stop (Figure 3)

SCL

SDA

START

CONDITION

Acknowledge Response from Receiver (Figure 4)

SCL FROM

MASTER

1

DATA OUTPUT

FROM

TRANSMITTER

DATA OUTPUT

FROM

RECEIVER

START

6

NM24C65U Rev. B.1

DS800012-5

STOP

CONDITION

8

9

DS800012-6

ACKNOWLEDGE

DS800012-7

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