NT5DS16M16CS View Datasheet(PDF) - NanoAmp Solutions, Inc.

Part Name

Description

Manufacturer

NT5DS16M16CS

256Mb DDR Synchronous DRAM

NanoAmp Solutions, Inc. 

NanoAmp Solutions, Inc.

NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT

NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS

Extended Mode Register

The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions

include DLL enable/disable, bit A0; output drive strength selection, bit A1; and QFC output enable/disable, bit A2 (optional).

These functions are controlled via the bit settings shown in the Extended Mode Register Definition. The Extended Mode

Register is programmed via the Mode Register Set command (with BA0 = 1 and BA1 = 0) and retains the stored information

until it is programmed again or the device loses power. The Extended Mode Register must be loaded when all banks are idle,

and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements

result in unspecified operation.

DLL Enable/Disable

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to nor-

mal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically disabled when

entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled,

200 clock cycles must occur to allow time for the internal clock to lock to the externally applied clock before a Read command

can be issued. This is the reason for introducing timing parameter tXSRD for DDR SDRAM’s (Exit Self Refresh to Read Com-

mand). Non- Read commands can be issued 2 clocks after the DLL is enabled via the EMRS command (tMRD) or 10 clocks after

the DLL is enabled via self refresh exit command (tXSNR, Exit Self Refresh to Non-Read Command).

Output Drive Strength

The normal drive strength for all outputs is specified to be SSTL_2, Class II.

QFC Enable/Disable

The QFC signal is an optional DRAM output control used to isolate module loads (DIMMs) from the system memory bus by

means of external FET switches when the given module (DIMM) is not being accessed. The QFC function is an optional feature

and is not included on all DDR SDRAM devices.

DOC # 14-02-044 Rev A ECN # 01-1116

13

The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com

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