NT5DS16M16CS-6K View Datasheet(PDF) - NanoAmp Solutions, Inc.

Part Name

Description

Manufacturer

NT5DS16M16CS-6K

256Mb DDR Synchronous DRAM

NanoAmp Solutions, Inc. 

NanoAmp Solutions, Inc.

Operations

NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT

NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS

Bank/Row Activation

Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank must be “opened”

(activated). This is accomplished via the Active command and addresses A0-A12, BA0 and BA1 (see Activating a Specific Row

in a Specific Bank), which decode and select both the bank and the row to be activated. After opening a row (issuing an Active

command), a Read or Write command may be issued to that row, subject to the tRCD specification. A subsequent Active com-

mand to a different row in the same bank can only be issued after the previous active row has been “closed” (precharged). The

minimum time interval between successive Active commands to the same bank is defined by tRC. A subsequent Active com-

mand to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access

overhead. The minimum time interval between successive Active commands to different banks is defined by tRRD.

Activating a Specific Row in a Specific Bank

CK

CK

CKE

CS

RAS

CAS

WE

A0-A12

BA0, BA1

HIGH

RA

BA

RA = row address.

BA = bank address.

Don’t Care

DOC # 14-02-044 Rev A ECN # 01-1116

19

The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com

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