NTE21256 View Datasheet(PDF) - NTE Electronics

Part Name

Description

Manufacturer

NTE21256

262,144–Bit Dynamic Random Access Memory (DRAM)

NTE Electronics 

AC Characteristics (Cont’d): (TA = 0° to +70°C, VCC = 5V ±10%, Note 9, Note 10, Note 11

unless otherwise specified)

Parameter

Symbol Test Conditions Min Typ Max Unit

Write Command Setup Time

Write Command Hold Time

Write Command Hold Time referenced to RAS

Write Command Pulse Width

Write Command to RAS Lead Time

Write Command to CAS Lead Time

Data in Setup Time

Data in Hold Time

Data in Hold Time referenced to RAS

CAS to WE Delay

RAS to WE Delay

RMW Cycle RAS Pulse Width

RMW Cycle CAS Pulse Width

Page Mode Cycle Time

Page Mode Read–Write Cycle Time

Page Mode CAS Precharge Time

tWCS

tWCH

tWCR

tWP

tRWL

tCWL

tDS

tDH

tDHR

tCWD

tRWD

tRRW

tCRW

tPC

tPRWC

tCP

Note 20

Note 17

Note 21

Note 21

Note 17

Note 20

Note 20

Note 12

0–

45 –

120 –

45 –

45 –

45 –

0–

45 –

120 –

75 –

150 –

200 –

125 –

145 –

190 –

60 –

– ns

– ns

– ns

– ns

– ns

– ns

– ns

– ns

– ns

– ns

– ns

– ns

– ns

– ns

– ns

– ns

Note 9. VIH and VIL are reference levels to measure timing of input signals. Also, transition times

are measured between VIH and VIL.

Note10. An initial pause of 200µs is required after power–up followed by a minimum of eight initialization

cycles prior to normal operation.

Note 11. The time parameters specified here are valid for a transition time of tT = 5ns for the input signals

Note12. The specification for tRC (Min), tRWC (Min), and page–mode cycle time (tPC) are only used

to indicate cycle time at which proper operation over full temperature range

(0°C ≤ TA ≤ +70°C) is assured.

Note17. tRCD + tCAH ≥ tAR Min, tRCD + tDH ≥ tDHR Min, tRCD + tWCH ≥ tWCR Min.

Note20. tWCS, tCWD, and tRWC are not restrictive operating parameters. They are included in the data

sheet as electrical characteristics only: If tWCS ≥ tWCS (Min), the cycle is an early write cycle

and the Data Out will remain open circuit (high impedance) throughout the entire cycle; if

tCWD ≥ tCWD (Min) and tRWD ≥ tRWD (Min) the cycle is a read–write cycle and the Data Out

will contain data read from the selected cell. If neither of the above sets of conditions is satis-

fied, the condition of the Data Out (at access time) is indeterminate.

Note21. tDS and tDH are referenced to the leading edge of CAS in early write cycles, and to the leading

edge of WE in delayed write of read–modify–write cycles.

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