ORT8850 View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

Manufacturer

ORT8850

Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver

Lattice Semiconductor 

Lattice Semiconductor

ORCA ORT8850 Data Sheet

ORT8850 Overview

The ORT8850 FPSCs provide high-speed backplane transceivers combined with FPGA logic. There are two

devices in the ORT8850 family. The ORT8850L device is based on 1.5 V OR4E02 ORCA FPGA and has a 26 x 24

array of Programmable Logic Cells (PLCs). The ORT8850H device is based on 1.5V OR4E06 ORCA FPGA and

has a 46 x 44 array. The embedded core which contains the backplane transceivers is attached to the right side of

the device and is integrated directly into the FPGA array. A top level diagram of the basic chip configuration is

shown in Figure 1.

Figure 1. ORT8850 Top Level Diagram

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Embedded

Core

Containing

8 Serial I/O

Channels

Embedded Core Overview

The ORT8850 embedded core contains a pseudo-SONET block for backplane or intra-board, chip-to-chip commu-

nication. The SONET block includes a High-Speed Interface (HSI) macrocell and a Synchronous Transport Module

(STM) macrocell. It supports eight full-duplex channels and performs data transfer, scrambling/descrambling and

SONET framing at the maximum rate of 850 Mbits/s. Figure 2 shows a top level diagram of the ORT8850 and the

basic data flows through the device.

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