HFA1110/883 View Datasheet(PDF) - Intersil
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HFA1110/883 Datasheet PDF : 13 Pages
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HFA1110/883
PC Board Layout
Evaluation Board
The frequency response of this buffer depends greatly on
the amount of care taken in designing the PC board. The
use of low inductance components such as chip resis-
tors and chip capacitors is strongly recommended,
while a solid ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10µF) tantalum in parallel with a small value
(0.1µF) chip capacitor works well in most cases.
The performance of this buffer may be evaluated using the
HFA1110 Evaluation Board. The layout and schematic of the
board are shown in Figure 25.
To order evaluation boards, please contact your local sales
office.
TOP LAYOUT
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
1
next section. Removing the GND plane under the output
trace helps minimize this capacitance.
An example of a good high frequency layout is the Evalua-
tion Board shown in Figure 25.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the buffer’s phase
margin resulting in frequency response peaking and possi-
ble oscillations. In most cases, the oscillation can be avoided
by placing a resistor (RS) in series with the output prior to
the capacitance.
Figure 24 details starting points for the selection of this resis-
tor. The points on the curve indicate the RS and CL combina-
tions for the optimum bandwidth, stability, and settling time,
but experimental fine tuning is recommended. Picking a
point above or to the right of the curve yields an overdamped
response, while points below or left of the curve indicate
areas of underdamped performance.
RS and CL form a low pass network at the output, thus limit-
ing system bandwidth well below the buffer bandwidth of
750MHz. By decreasing RS as CL increases (as illustrated in
Figure 24), the maximum bandwidth is obtained without sac-
rificing stability. Even so, bandwidth does decrease as you
move to the right along the curve.
BOTTOM LAYOUT
50
45
40
35
30
25
20
15
10
5
0
0
40 80 120 160 200 240 280 320 360 400
LOAD CAPACITANCE (pF)
FIGURE 24. RECOMMENDED SERIES OUTPUT RESISTOR vs
LOAD CAPACITANCE
+5V
0.1µF
IN
10µF
50Ω
1
2
HFA1110
3
4
50Ω
8
7
RS
6
5
10µF
OUT
-5V
0.1µF
FIGURE 25. EVALUATION BOARD SCHEMATIC AND LAYOUT
Spec Number 511083-883
10
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