P89LPC932A1 View Datasheet(PDF) - Philips Electronics

Part Name

Description

Manufacturer

P89LPC932A1

8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 512-byte data EEPROM

Philips Electronics 

Philips Semiconductors

P89LPC932A1

8-bit microcontroller with accelerated two-clock 80C51 core

• CODE

64 kB of Code memory space, accessed as part of program execution and via the

MOVC instruction. The P89LPC932A1 has 8 kB of on-chip Code memory.

The P89LPC932A1 also has 512 bytes of on-chip Data EEPROM that is accessed via

SFRs (see Section 7.27 “Data EEPROM”).

7.11 Data RAM arrangement

The 768 bytes of on-chip RAM are organized as shown in Table 5.

Table 5:

Type

DATA

IDATA

XDATA

On-chip data memory usages

Data RAM

Memory that can be addressed directly and indirectly

Memory that can be addressed indirectly

Auxiliary (‘External Data’) on-chip memory that is accessed

using the MOVX instructions

Size (bytes)

128

256

512

7.12 Interrupts

The P89LPC932A1 uses a four priority level interrupt structure. This allows great flexibility

in controlling the handling of the many interrupt sources. The P89LPC932A1 supports

15 interrupt sources: external interrupts 0 and 1, timers 0 and 1, serial port Tx, serial port

Rx, combined serial port Rx/Tx, brownout detect, watchdog/RTC, I2C-bus, keyboard,

comparators 1 and 2, SPI, CCU, and data EEPROM write completion.

Each interrupt source can be individually enabled or disabled by setting or clearing a bit in

the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global

disable bit, EA, which disables all interrupts.

Each interrupt source can be individually programmed to one of four priority levels by

setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An

interrupt service routine in progress can be interrupted by a higher priority interrupt, but

not by another interrupt of the same or lower priority. The highest priority interrupt service

cannot be interrupted by any other interrupt source. If two requests of different priority

levels are pending at the start of an instruction, the request of higher priority level is

serviced.

If requests of the same priority level are pending at the start of an instruction, an internal

polling sequence determines which request is serviced. This is called the arbitration

ranking. Note that the arbitration ranking is only used to resolve pending requests of the

same priority level.

7.12.1 External interrupt inputs

The P89LPC932A1 has two external interrupt inputs as well as the Keypad Interrupt

function. The two interrupt inputs are identical to those present on the standard 80C51

microcontrollers.

These external interrupts can be programmed to be level-triggered or edge-triggered by

setting or clearing bit IT1 or IT0 in Register TCON.

9397 750 14871

Product data sheet

Rev. 02 — 10 May 2005

© Koninklijke Philips Electronics N.V. 2005. All rights reserved.

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