ADV7176A View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADV7176A Datasheet PDF : 50 Pages
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ADV7175A/ADV7176A
5 V TIMING SPECIFICATIONS (VAA = 4.75 V–5.25 V1, VREF = 1.235 V, RSET = 150 ⍀. All specifications TMIN to TMAX2 unless
otherwise noted.)
Parameter
Conditions
Min Typ Max Unit
MPU PORT3, 4
SCLOCK Frequency
0
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
4.0
4.7
After This Period the First Clock Is Generated 4.0
Relevant for Repeated Start Condition
4.7
250
4.7
ANALOG OUTPUTS3, 5
Analog Output Delay
5
DAC Analog Output Skew
0
100 kHz
µs
µs
µs
µs
ns
1
µs
300 ns
µs
ns
ns
CLOCK CONTROL
AND PIXEL PORT3, 6
FCLOCK
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t11
Data Hold Time, t12
Control Setup Time, t11
Control Hold Time, t12
Digital Output Access Time, t13
Digital Output Hold Time, t14
Pipeline Delay, t15
TELETEXT PORT3, 7
Digital Output Access Time, t16
Data Setup Time, t17
Data Hold Time, t18
RESET CONTROL3, 4
RESET Low Time
27
MHz
8
ns
8
ns
3.5
ns
4
ns
4
ns
3
ns
24
ns
4
ns
37
Clock Cycles
20
ns
1
ns
2
ns
6
ns
NOTES
1The max/min specifications are guaranteed over this range.
2Temperature range TMIN to TMAX: 0°C to 70°C.
3TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load ≤ 10 pF.
4Guaranteed by characterization.
5Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6Pixel Port consists of the following:
Pixel Inputs:
Pixel Controls:
P15–P0
HSYNC, FIELD/VSYNC, BLANK
Clock Input:
CLOCK
7Teletext Port consists of the following:
Teletext Output:
TTXREQ
Teletext Input:
TTX
Specifications subject to change without notice.
–6–
REV. C
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