P89LPC932A1FA View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

P89LPC932A1FA

8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 512-byte data EEPROM

NXP Semiconductors. 

NXP Semiconductors

P89LPC932A1

8-bit microcontroller with accelerated two-clock 80C51 core

I In-Circuit Programming (ICP) allows simple production coding with commercial

EPROM programmers. Flash security bits prevent reading of sensitive application

programs.

I Serial flash In-System Programming (ISP) allows coding while the device is mounted

in the end application.

I In-Application Programming (IAP) of the flash code memory. This allows changing the

code in a running application.

I Watchdog timer with separate on-chip oscillator, requiring no external components.

The watchdog prescaler is selectable from eight values.

I Low voltage reset (brownout detect) allows a graceful system shutdown when power

fails. May optionally be configured as an interrupt.

I Idle and two different power-down reduced power modes. Improved wake-up from

Power-down mode (a LOW interrupt input starts execution). Typical power-down

current is 1 µA (total power-down with voltage comparators disabled).

I Active-LOW reset. On-chip power-on reset allows operation without external reset

components. A reset counter and reset glitch suppression circuitry prevent spurious

and incomplete resets. A software reset function is also available.

I Configurable on-chip oscillator with frequency range options selected by user

programmed flash configuration bits. Oscillator options support frequencies from

20 kHz to the maximum operating frequency of 18 MHz.

I Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator

allowing it to perform an oscillator fail detect function.

I Programmable port output configuration options: quasi-bidirectional, open drain,

push-pull, input-only.

I Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of

the pins match or do not match a programmable pattern.

I LED drive capability (20 mA) on all port pins. A maximum limit is specified for the

entire chip.

I Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns

minimum ramp times.

I Only power and ground connections are required to operate the P89LPC932A1 when

internal reset option is selected.

I Four interrupt priority levels.

I Eight keypad interrupt inputs, plus two additional external interrupt inputs.

I Schmitt trigger port inputs.

I Second data pointer.

I Emulation support.

2.3 Comparison to the P89LPC932

The P89LPC932A1 includes several improvements compared to the P89LPC932. Please

see P89LPC932A1 User manual for additional detailed information.

I Byte-erasability has been added to the user code memory space.

I All of the errata described in the P89LPC932 Errata sheet have been fixed.

I Serial ICP has been added.

P89LPC932A1_3

Product data sheet

Rev. 03 — 12 March 2007

© NXP B.V. 2007. All rights reserved.

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