P89LPC932A1FN View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
P89LPC932A1FN
NXP Semiconductors.
P89LPC932A1FN Datasheet PDF : 64 Pages
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NXP Semiconductors
P89LPC932A1
8-bit microcontroller with accelerated two-clock 80C51 core
Table 2. Pin description …continued
Symbol
Pin
Type Description
TSSOP28, HVQFN28
PLCC28,
DIP28
P1.5/RST
6
2
I
P1.5 — Port 1 bit 5 (input only).
I
RST — External Reset input during power-on or if selected via UCFG1.
When functioning as a reset input, a LOW on this pin resets the
microcontroller, causing I/O ports and peripherals to take on their default
states, and the processor begins execution at address 0. Also used during
a power-on sequence to force ISP mode. When using an oscillator
frequency above 12 MHz, the reset input function of P1.5 must be
enabled. An external circuit is required to hold the device in reset at
power-up until VDD has reached its specified level. When system
power is removed VDD will fall below the minimum specified
operating voltage. When using an oscillator frequency above
12 MHz, in some applications, an external brownout detect circuit
may be required to hold the device in reset when VDD falls below the
minimum specified operating voltage.
P1.6/OCB
5
1
I/O P1.6 — Port 1 bit 6.
O OCB — Output Compare B.
P1.7/OCC
4
28
I/O P1.7 — Port 1 bit 7.
O OCC — Output Compare C.
P2.0 to P2.7
I/O Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type.
During reset Port 2 latches are configured in the input only mode with the
internal pull-up disabled. The operation of Port 2 pins as inputs and
outputs depends upon the port configuration selected. Each port pin is
configured independently. Refer to Section 7.13.1 “Port configurations”
and Table 8 “Static characteristics” for details.
All pins have Schmitt trigger inputs.
Port 2 also provides various special functions as described below:
P2.0/ICB
1
25
I/O P2.0 — Port 2 bit 0.
I
ICB — Input Capture B.
P2.1/OCD
2
26
I/O P2.1 — Port 2 bit 1.
O OCD — Output Compare D.
P2.2/MOSI 13
9
I/O P2.2 — Port 2 bit 2.
I/O MOSI — SPI master out slave in. When configured as master, this pin is
output; when configured as slave, this pin is input.
P2.3/MISO 14
10
I/O P2.3 — Port 2 bit 3.
I/O MISO — When configured as master, this pin is input, when configured as
slave, this pin is output.
P2.4/SS
15
11
I/O P2.4 — Port 2 bit 4.
I
SS — SPI Slave select.
P2.5/SPICLK 16
12
I/O P2.5 — Port 2 bit 5.
I/O SPICLK — SPI clock. When configured as master, this pin is output; when
configured as slave, this pin is input.
P2.6/OCA
27
23
I/O P2.6 — Port 2 bit 6.
O OCA — Output Compare A.
P89LPC932A1_3
Product data sheet
Rev. 03 — 12 March 2007
© NXP B.V. 2007. All rights reserved.
9 of 64
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