8 x 8 Video Crosspoint Switch
_______________________________________________Timing Diagrams (continued)
SEE FIGURE 4 FOR WR
AND LATCH TIMING
DATA (N)
DATA (N + 1)
DATA (N + 2)
WR
LATCH
FIRST-RANK REGISTER DATA
SECOND-RANK REGISTER DATA
(EDGE/LEVEL = Low)
SECOND-RANK REGISTER DATA
(EDGE/LEVEL = High)
DATA (N)
DATA (N + 1)
DATA (N + 2)
DATA (N)
DATA (N + 1)
DATA (N)
DATA (N + 1)
Figure 5. Parallel-Interface Mode Format (SER/ P–—A—R– = Low)
SEE TABLE 2 FOR
INPUT DATA
INPUT DATA FOR OUT0
INPUT DATA FOR OUT1 TO OUT6
INPUT DATA FOR OUT7
SEE FIGURE 4 FOR WR
AND LATCH TIMING
0D3
0D2
0D1
0D0
1D3
1D2
7D3
7D2
7D1
7D0
WR
LATCH
SECOND-RANK REGISTER DATA
(EDGE/LEVEL = Low)
SECOND-RANK REGISTER DATA
(EDGE/LEVEL = High)
Figure 6. 32-Bit Serial-Mode Interface Format (SER/P–—A—R– = High)
DATA VALID
DATA VALID
10 ______________________________________________________________________________________