PC8240VTPU200E View Datasheet(PDF) - Atmel Corporation
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Description
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PC8240VTPU200E Datasheet PDF : 42 Pages
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PC8240
The final die-junction operating temperature, is not only a function of the component-
level thermal resistance, but the system-level design and its operating conditions. In
addition to the component’s power consumption, a number of factors affect the final
operating die-junction temperature-airflow, board population (local heat flux of adjacent
components), heat sink efficiency, heat sink attach, heat sink placement, next-level
interconnect technology, system air temperature rise, altitude, etc.
Due to the complexity and the many variations of system-level boundary conditions for
today’s microelectronic equipment, the combined effects of the heat transfer mecha-
nisms (radiation, convection and conduction) may vary widely. For these reasons, we
recommend using conjugate heat transfer models for the board, as well as, system-level
designs. To expedite system-level thermal analysis, several “compact” thermal-package
models are available within FLOTHERM®. These are available upon request.
Power Consideration
Table 5 provides preliminary power consumption data for the PC8240.
At recommended operating conditions (see Table 3 on page 8) with GVdd = 3.3V ± 5%
and LVdd = 3.3V ± 5%
Table 5. Preliminary Power Consumption
PCI Bus Clock/Memory Bus Clock
CPU Clock Frequency (MHz)
Mode
33/66/166
33/66/200
33/100/200
Typical
2.5
2.8
3.0
Max – FP
3.0
3.4
3.6
Max – INT
2.7
3.0
3.3
Doze
1.8
2.0
2.2
Nap
700
700
900
Sleep
500
500
500
66/100/200
3.0
3.6
3.4
2.2
900
800
Unit
W
W
W
W
mW
mW
Notes
(1)(5)
(1)(2)
(1)(3)
(1)(4)(6)
(1)(4)(6)
(1)(4)(6)
I/O Power Supplies
Mode
Typ – OVdd
Typ – GVdd
Minimum
200
300
Maximum
600
900
Unit
mW
mW
Notes
(7)(8)
(7)(9)
Notes:
1. The values include Vdd, AVdd, AVdd2, and LVdd but do not include I/O Supply Power, see “Power Supply Sizing” on page
36 for information on OVdd and GVdd supply power.
2. Maximum – FP power is measured at Vdd = 2.625V with dynamic power management enabled while running an entirely
cacheresident, looping, floating point multiplication instruction.
3. Maximum – INT power is measured at Vdd = 2.625V with dynamic power management enabled while running entirely
cache-resident, looping, integer instructions.
4. Power saving mode maximums are measured at Vdd = 2.625V while the device is in doze, nap, or sleep mode.
5. Typical power is measured at Vdd = AVdd = 2.5V, OVdd = 3.3V where a nominal FP value, a nominal INT value, and a
value where there is a continuous flush of cache lines with alternating ones and zeroes on 64-bit boundaries to local mem-
ory are averaged.
6. Power saving mode data measured with only two PCI_CLKs and two SDRAM_CLKs enabled.
7. The typical minimum I/O power values were results of the PC8240 performing cache resident integer operations at the slow-
est frequency combination of 33:66:166 (PCI:Mem:CPU) MHz.
8. The typical maximum OVdd value resulted from the PC8240 operating at the fastest frequency combination of 66:100:200
(PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with alternating ones and zeroes to PCI memory.
15
2149A–HIREL–05/02
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