PCA84C846 View Datasheet(PDF) - Philips Electronics

Part Name

Description

Manufacturer

PCA84C846

Microcontrollers for TV tuning control and OSD applications

Philips Electronics 

Philips Semiconductors

Microcontrollers for TV tuning

control and OSD applications

Preliminary specification

PCA84C646; PCA84C846

9 OSD (ON SCREEN DISPLAY) FUNCTION

9.3 Vertical display position control

9.1 Features

• Display RAM: 64 × 10 bit.

• Display character fonts: 64 (in which 62 customized +

2 special reserved codes).

• Display starting position (of the first character):

64 different positions by software control, both vertical

and horizontal.

• Character size: 4 different character sizes, line-by-line

basis, 1 dot = 1H/1V, 2H/2V, 3H/3V, 4H/4V.

• Character matrix: 12 × 18 with no spacing between

characters.

• Foreground colours: 8, combination of Red, Green, Blue;

character-by-character basis.

• Background/shadowing modes: 4, No background,

Box shadowing, North-west shadowing,

Frame shadowing (raster blanking), frame basis.

• Background colours: 8, combination of Red, Green,

Blue; word-by-word basis. Available when background

mode is either in Box shadowing or North-west

shadowing and Frame shadowing mode.

• On-chip OSD oscillator.

• Character blinking rate: 1 : 1, 1 : 3, 3 : 1 (frequency:

1⁄16, 1⁄32, 1⁄64 or 1⁄128 of fVSYNC, programmable,

e.g. NTSC: 60⁄16 Hz, PAL: 50⁄64 Hz etc.); character basis.

• Display format: flexible display format by using Carriage

Return (CR) code, maximum number of characters per

line is flexible and depending on the OSD clock.

• Spacing between lines: 4 different choices from 0, 4,

8 or 12 horizontal scan lines.

• Display character RAM auto-address-post-increment

when writing data.

• Programmable HSYNC and VSYNC active input polarity.

• Programmable G (VOW1), B (VOW2), R (VOW0) and

FB (VOB) output polarity.

9.2 Horizontal display position control

The horizontal position counter is increased every OSD

clock (fOSD) cycle after the programmed level of HSYNC

occurs at the HSYNC pin and is reset when the opposite

polarity of the HSYNC is reached. Horizontal start position

is controlled by Derivative Register 36 (HPOS;

see Table 36). The starting position is calculated as:

HP = [4 × (H5 to H0) + 5] × (OSD clock cycle)

where (H5 to H0) = decimal value of register HPOS;

(H5 to H0) ≥ 10.

The vertical position counter is increased every HSYNC

cycle and is reset by the VSYNC signal. Vertical start

position is controlled by Derivative Register 35 (VPOS;

see Table 34). The vertical starting position is calculated

as:

VP = [4 × (V5 to V0)] × (horizontal scan lines)

where (V5 to V0) = decimal value of register VPOS;

(V5 to V0) ≥ 0.

9.4 Clock generator

Figure 12 illustrates the block diagram of the on-chip OSD

clock generator which consists of a Phased-Lock Loop

(PLL) circuit. The Voltage Controlled Oscillator (VCO)

outputs a clock (fVCO) with a frequency range of

8 to 20 MHz (see Fig.12). The input signal f1 = HSYNC.

The programmable active level detector:

• Passes signal f1, when HSYNC is active HIGH, or

• Inverts signal f1, when HSYNC is active LOW.

The output signal f2 is always active HIGH. The VCO is

synchronized with the HIGH-to-LOW edge of the f2 signal.

The value programmed in the 7-bit PLL Programmable

Counter control register (PLLCN; Derivative Register 25;

see Table 40) determines:

fVCO = f1 × 16 × (decimal value of 7-bit counter);

where 16 < (decimal value of 7-bit counter) < 48.

The value 16 is the 4-bit prescaler which increases or

decreases the output of the VCO in steps of (16 × f1).

Given an example of f1 = 15.750 kHz, the fVCO is then

increased or decreased in steps of

16 × 15.750 kHz = 252 kHz = 0.25 MHz.

The fVCO is fed into a buffer to generate the OSD dot clock

frequency signal (fOSD); 4 MHz ≤ fOSD ≤ 12 MHz.

Decreasing fOSD gives broader characters.

Recommended: 4 MHz ≤ fOSD typical ≤ 12 MHz.

The OSD clock is enabled/disabled by the state of the EN

bit (Derivative Register 34; see also Section 12.4). When

the OSD clock is disabled (fOSD = LOW) the oscillator

remains active, therefore the transient time from the OSD

clock start-up to locking into the external HSYNC signal is

reduced.

As the on-chip oscillator is always active after Power-on,

when the OSD clock is enabled no large currents flow (as

for RC or LC oscillators) and therefore radiated noise is

dramatically reduced.

1995 Jun 15

16

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