PCA9505 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
PCA9505 Datasheet PDF : 31 Pages
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NXP Semiconductors
PCA9505/06
40-bit I2C-bus I/O port with RESET, OE and INT
Table 3. Register summary …continued
Register # D5 D4 D3 D2 D1 D0 Symbol
(hex)
Mask Interrupt registers
20
1 0 0 0 0 0 MSK0
21
1 0 0 0 0 1 MSK1
22
1 0 0 0 1 0 MSK2
23
1 0 0 0 1 1 MSK3
24
1 0 0 1 0 0 MSK4
25
100101-
26
100110-
27
100111-
Access
read/write
read/write
read/write
read/write
read/write
-
-
-
Description
Mask Interrupt register bank 0
Mask Interrupt register bank 1
Mask Interrupt register bank 2
Mask Interrupt register bank 3
Mask Interrupt register bank 4
reserved for future use
reserved for future use
reserved for future use
7.3.1 IP0 to IP4 - Input Port registers
These registers are read-only. They reflect the incoming logic levels of the port pins
regardless of whether the pin is defined as an input or an output by the I/O Configuration
register. If the corresponding Px[y] bit in the PI registers is set to logic 0, or the inverted
incoming logic levels if the corresponding Px[y] bit in the PI register is set to logic 1. Writes
to these registers have no effect.
Table 4. IP0 to IP4 - Input Port registers (address 00h to 04h) bit description
Legend: * default value ‘X’ determined by the externally applied logic level.
Address Register
Bit
Symbol
Access Value
00h
IP0
7 to 0
I0[7:0]
R
XXXX XXXX*
01h
IP1
7 to 0
I1[7:0]
R
XXXX XXXX*
02h
IP2
7 to 0
I2[7:0]
R
XXXX XXXX*
03h
IP3
7 to 0
I3[7:0]
R
XXXX XXXX*
04h
IP4
7 to 0
I4[7:0]
R
XXXX XXXX*
Description
Input Port register bank 0
Input Port register bank 1
Input Port register bank 2
Input Port register bank 3
Input Port register bank 4
The Polarity Inversion register can invert the logic states of the port pins. The polarity of
the corresponding bit is inverted when Px[y] bit in the PI register is set to logic 1. The
polarity of the corresponding bit is not inverted when Px[y] bits in the PI register is set to
logic 0.
PCA9505_9506_3
Product data sheet
Rev. 03 — 6 June 2007
© NXP B.V. 2007. All rights reserved.
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