PCA9509P(2012) View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
PCA9509P Datasheet PDF : 23 Pages
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NXP Semiconductors
PCA9509P
Low power level translating I2C-bus/SMBus repeater
7. Application design-in information
A typical application is shown in Figure 4. In this example, the CPU is running on a 0.9 V
I2C-bus while the slave is connected to a 3.3 V bus. Both buses run at 400 kHz. Master
devices can be placed on either bus.
0.9 V
3.3 V
10 kΩ
VCC(A) VCC(B)
SDA
A1
B1
SCL
A2
B2
MASTER
CPU
0.9 V
PCA9509P
10 kΩ
EN
10 kΩ
SDA
SCL
SLAVE
400 kHz
bus A
bus B
002aag176
Fig 4. Typical application
When port B of the PCA9509P is pulled LOW by a driver on the I2C-bus, a CMOS
hysteresis input detects the falling edge when it goes below 0.3VCC(B) and causes the
internal driver on port A to turn on, causing port A to pull down to about 0.2VCC(A). When
port A of the PCA9509P falls, a comparator detects the falling edge when it falls below
0.15VCC(A) and causes the internal driver on port B to turn on and pull the port B pin down
to ground. In order to illustrate what would be seen in a typical application, refer to
Figure 5 and Figure 6. If the bus master in Figure 4 were to write to the slave through the
PCA9509P, waveforms shown in Figure 5 would be observed on the B bus. This looks
like a normal I2C-bus transmission.
On the A bus side of the PCA9509P, the clock and data lines would have a positive offset
from ground equal to the VOL of the PCA9509P. After the 8th clock pulse, the data line will
be pulled to the VOL of the master device, which is very close to ground in this example. At
the end of the acknowledge, the level rises only to the LOW level set by the driver in the
PCA9509P for a short delay while the B bus side rises above 0.5VCC(B), then it continues
HIGH. It is important to note that any arbitration or clock stretching events require that the
LOW level on the A bus side at the input of the PCA9509P (VIL) is below 0.1VCC(A) to be
recognized by the PCA9509P and then transmitted to the B bus side.
9th clock pulse
acknowledge
SCL
SDA
PCA9509P
Product data sheet
Fig 5. Bus B SMBus/I2C-bus waveform
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 August 2012
002aab644
© NXP B.V. 2012. All rights reserved.
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