PCA9509P View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

PCA9509P

Low power level translating I2C-bus/SMBus repeater

NXP Semiconductors. 

NXP Semiconductors

PCA9509P

Low power level translating I2C-bus/SMBus repeater

The enable pin should only change state when the bus and the repeater port are in an idle

state to prevent system failures.

Because the enable pin (EN) can put the PCA9509P in Standby mode, and when in

standby the current mirrors are turned OFF to save power, the recovery from the

disabled/standby state is slow so that the current mirrors can return to full current before

the channels are enabled.

Remark: The system design should allow sufficient time after STOP before disabling the

PCA9509P so that both sides of the SDA and SCL channels are HIGH. It should also

allow sufficient time before the START such that the channel is disabled before the SDA

goes LOW. The PCA9509P should only be enabled during a bus idle state and there also

must be sufficient time allowed before the START such that the PCA9509P is fully active

before the falling edge of the SDA that defines a START.

6.2 I2C-bus systems

As with the standard I2C-bus system, pull-up resistors are required to provide the logic

HIGH levels. The size of these pull-up resistors depends on the system. Port A is

designed to work with pull-up resistor’s size as required to meet rise time requirements

but minimize current consumption. Port B is designed to work with Standard-mode and

Fast-mode I2C-bus devices in addition to SMBus devices. Standard-mode I2C-bus

devices only specify 3 mA output drive; this limits the termination current to 3 mA in a

generic I2C-bus system where Standard-mode devices and multiple masters are possible.

Under certain conditions higher termination currents can be used (when all currents are

> 3 mA).

6.3 Edge rate control

The PCA9509P includes circuitry that slows down the falling edge of both the A side and

B side open-drain output pull-downs. This slowdown reduces system noise and

undershoot when the signal reflects off of the end of the bus. The slew rate control circuit

limits the maximum slew rate, and is relatively insensitive to the load capacitance, the bus

high voltage and to the pull-up value. The rising edge slew rate on the A side and B side is

controlled by RC time constant of the bus pull-up resistor and the bus capacitance, which

are system level considerations and not under the control of the PCA9509P. The pull-up

resistors should be chosen based on the total bus capacitance to result in a reasonable

rising edge transition time that is less than the maximum allowed rise time, and slow

enough not to make system level noise problems, and to make the A side low voltage less

than VIL.

6.4 Bus pull-up resistor selection

The AC test load for the PCA9509P is 1.35 k and 50 pF total capacitance. This results in

a rise time of approximately 60 ns. The 1.35 k resistor is chosen to provide a little less

than 3 mA in a 3.3 V application so it is compatible with Standard-mode I2C-bus devices

as well as Fast-mode devices. The B side output pull-down is a strong driver and is

capable of sinking Fast-mode Plus (Fm+) currents, however the pull-up must be sized for

the weakest part in the system, so if Standard-mode I2C-bus parts are present on the

B side, the pull-up must be limited to less than 3 mA. If only Fm+ parts are used on the

B side, the maximum pull-up current may be up to 30 mA. The pull-up resistor should

always be sized to provide less than the rated pull-up current for the weakest part on the

bus under the maximum bus voltage expected in the system. When the bus capacitance

PCA9509P

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4 — 18 May 2018

© NXP B.V. 2018. All rights reserved.

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