PC85132/232-1 View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

PC85132/232-1

LCD driver for low multiplex rates

NXP Semiconductors. 

NXP Semiconductors

PCA85132

LCD driver for low multiplex rates

acknowledge cycle is required, it is therefore necessary to minimize the track resistance

from the SDAACK pin to the system SDA line to guarantee a valid LOW level (see

Section 14.2 on page 42).

By separating the acknowledge output from the serial data line (having the SDAACK open

circuit) design efforts to generate a valid acknowledge level can be avoided. However, in

that case the I2C-bus master has to be set up in such a way that it ignores the

acknowledge cycle.2

The following definition assumes that SDA and SDAACK are connected and refers to the

pair as SDA.

8.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

are interpreted as a control signal (see Figure 17).

SDA

SCL

Fig 17. Bit transfer

data line

stable;

data valid

change

of data

allowed

mba607

8.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change

of the data line, while the clock is HIGH is defined as the START condition (S).

A LOW-to-HIGH change of the data line while the clock is HIGH is defined as the STOP

condition (P). The START and STOP conditions are shown in Figure 18.

SDA

SDA

SCL

S

START condition

Fig 18. Definition of START and STOP conditions

P

STOP condition

SCL

mbc 622

8.2 System configuration

A device generating a message is a transmitter; a device receiving a message is the

receiver. The device that controls the message is the master and the devices which are

controlled by the master are the slaves. The system configuration is shown in Figure 19.

2. For further information, please consider the NXP application note: Ref. 1 “AN10170”.

PCA85132

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4 — 9 April 2015

© NXP Semiconductors N.V. 2015. All rights reserved.

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