PCA8537 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
PCA8537 Datasheet PDF : 82 Pages
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NXP Semiconductors
PCA8537
Automotive LCD driver for multiplex rates up to 1:8
8.1.12.1 Timing and frame frequency
The timing of the PCA8537 organizes the internal data flow of the device. This includes
the transfer of display data from the display RAM to the display segment outputs. The
timing also generates the LCD frame frequency. The frame frequency is a fixed division of
the internal clock or of the frequency applied to pin CLK when an external clock is used.
When the internal clock is used, the clock frequency can be programmed by software
such that the nominal frame frequency can be chosen in steps of 10 Hz in the range of
60 Hz to 300 Hz (see Table 18). Furthermore the nominal frame frequency is
factory-calibrated with an accuracy of ±15 %.
When the internal clock is enabled at pin CLK by using bit COE, the duty ratio of the clock
may change when choosing different values for the frame frequency prescaler. Table 18
shows the different output duty ratios for each frame frequency prescaler setting.
8.1.13 Command: Bank-select
For the multiplex drive modes 1:4, 1:2, and the static drive mode, it is possible to write
data to one area of the RAM while displaying from another. These areas are named RAM
banks. There are two banks, 0 and 1. Figure 39 on page 49 and Figure 40 on page 49
show the concept. The Bank-select command controls where data is written to and where
it is displayed from.
Table 19. Bank-select - bank select command bit description
For further information, see Section 8.9 on page 49.
Bit
Symbol
Binary value Description
7 to 2 -
0000 10
fixed value
1
IBS
selects RAM bank to write to
0[1]
Bank 0
1
Bank 1
0
OBS
selects RAM bank to read from to the LCD
0[1]
Bank 0
1
Bank 1
[1] Default value.
8.1.14 Command: Write-RAM-data
By setting the RS bit of the control byte to logic 1, all data transferred is interpreted as
RAM data and placed in the RAM in accordance with the current setting of the RAM
address pointer (see Section 8.1.11 on page 12). Definition of the RS can be found in
Table 31 on page 50.
Remark: After Power-On Reset (POR) the RAM content is random and should be brought
to a defined status by clearing it (setting it to logic 0).
Table 20. Write-RAM-data - write RAM data command bit description
For further information, see Section 8.8 on page 43.
Bit
Symbol
Binary value Description
7 to 0 B[7:0]
00000000 to writing data byte-wise to the RAM
11111111
PCA8537
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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