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PCA9518 View Datasheet(PDF) - NXP Semiconductors.

Part Name
Description
Manufacturer
PCA9518
NXP
NXP Semiconductors. NXP
PCA9518 Datasheet PDF : 21 Pages
First Prev 11 12 13 14 15 16 17 18 19 20
NXP Semiconductors
PCA9518
Expandable 5-channel I2C-bus hub
10. Dynamic characteristics
Table 5.
Symbol
tPHL
Dynamic characteristics
Parameter
HIGH to LOW propagation delay
tPLH
LOW to HIGH propagation delay
tPHL1
HIGH to LOW propagation delay 1
tPLH1
LOW to HIGH propagation delay 1
tPLH2
LOW to HIGH propagation delay 2
tTHL
HIGH to LOW output transition time
tTLH
LOW to HIGH output transition time
tsu
set-up time
th
hold time
Conditions
SDA to SDAn, or
SCL to SCLn; Figure 7
SDA to SDAn, or
SCL to SCLn; Figure 7
EXPSDA1 to SDA, or
EXPSCL1 to SCL; Figure 7
EXPSDA1 to SDA, or
EXPSCL1 to SCL; Figure 7
EXPSDA2 to SDA, or
EXPSCL2 to SCL; Figure 7
SDA, SCL; Figure 7
SDA, SCL; Figure 7
enable to START condition
enable after STOP condition
Min
[1][2] 105
[1][3] 110
109
130
160
58
-
300
300
Typ
Max Unit
202
389 ns
259
265 ns
193
327 ns
153
179 ns
234
279 ns
110
187 ns
0.85 RC -
ns
-
-
ns
-
-
ns
[1] The SDA and SCL propagation delays are dominated by rise times or fall times. The fall times are mostly internally controlled and are
only sensitive to load capacitance. The rise times are RC time constant controlled and therefore a specific numerical value can only be
given for fixed RC time constants.
[2] The SDA HIGH to LOW propagation delay includes the fall time from VCC to 0.5VCC of the EXPSDA1 or EXPSCL1 pins and the SDA or
SCL fall time from the quiescent HIGH (usually VCC) to below 0.3VCC. The SDA and SCL outputs have edge rate control circuits
included which make the fall time almost independent of load capacitance.
[3] The SDA or SCL LOW to HIGH propagation delay includes the rise time constant from the quiescent LOW to 0.5VCC for the EXPSDA1
or EXPSCL2, the rise time constant for the quiescent LOW to 0.5VCC for the EXPSDA1 or EXPSCL1, and the rise time constant from
the quiescent external driven LOW to 0.7VCC for the SDA or SCL output. All of these rise times are RC time constants determined by the
external resistance and total capacitance for the various nodes.
PCA9518_5
Product data sheet
input SDA or SCL
0.7VCC
tTHL
0.3VCC
0.4 V
tPHL
tPHL1
0.3VCC
0.4 V
effective
stretch
tTLH
0.7VCC
EXPSDA1 or EXPSCL1
0.5VCC
tPHL2
0.5VCC
tPLH2
EXPSDA2 or EXPSCL2
output SDA or SCL
Fig 7. AC waveforms
0.5VCC
0.5VCC
tPHL1
0.7VCC
0.52 V
tTHL
0.3VCC
tTLH
0.3VCC
Rev. 05 — 2 December 2008
tPLH
tPLH1
tPLH2
0.7VCC
002aae328
© NXP B.V. 2008. All rights reserved.
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