PCA9525 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
PCA9525 Datasheet PDF : 22 Pages
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NXP Semiconductors
PCA9525
Simple 2-wire bus buffer
5
VI
(V)
4
002aaf333
3
Vlock
2
VIH
1
VIL
0
2
3
4
5
6
VDD (V)
Tamb = 25 °C
Fig 5. Typical input levels versus supply voltage
1000
VI(hys)
(V)
800
600
400
Tamb = +85 °C
+25 °C
−40 °C
200
0
2
3
4
002aaf334
5
6
VDD (V)
Fig 6. Typical VIH − VIL hysteresis versus supply
voltage
100
VOL
(mV)
80
60
002aaf335
300
VOL
(mV)
200
VDD = 5.5 V
2.7 V
002aaf336
40
20 VDD = 5.5 V
2.7 V
0
0
2
4
6
8
10
RPU (kΩ)
Fig 7.
Tamb = 25 °C
Typical LOW-level output voltage versus
pull-up resistance
100
0
−50
0
50
100
150
Tamb (C)
Fig 8.
IOL = 4 mA
Typical LOW-level output voltage versus
ambient temperature
9.1 Bidirectional data buffer
The bidirectional data buffer will determine which side has first fallen below Vlock and give
that side of the buffer control over the direction of the buffer. For the purpose of this one
LOW-going pulse, that side now becomes the ‘input’ (be it SDA_IN or SDA_OUT).
When the ‘input’ side falls to near VIL, it will begin to drive the ‘output’ side of the buffer
LOW. It will continue to hold the ‘output’ low until the ‘input’ exceeds VIH at which point the
‘output’ is released and will rise as fast as it is permitted by the load and pull-up to which it
is attached. (Assuming, of course, that the ‘output’ is not otherwise held LOW by some
other device on the bus on that side of the buffer.)
When the ‘input’ side again exceeds Vunlock, it will release its control of the buffer direction.
At this point, if the ‘output’ side was being held LOW (< Vlock) by another device, it will
immediately gain control and now become the ‘input’. What was the ‘input’ will now
become the ‘output’, and the process will repeat as above, but in the opposite direction.
PCA9525
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 25 February 2011
© NXP B.V. 2011. All rights reserved.
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