PCD3359A View Datasheet(PDF) - Philips Electronics
Part Name
Description
Manufacturer
PCD3359A Datasheet PDF : 32 Pages
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Philips Semiconductors
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
Product specification
PCD3359A
Table 18 Page setup; preset
INSTRUCTION
MOV A, #addr
MOV ADDR, A
MOV A, #data
MOV DATR, A
RESULT
address of EEPROM latch
send address to ADDR
load write, erase/write or erase data
send data to addressed EEPROM
latch
Table 19 Page setup; auto-incrementing
INSTRUCTION
MOV A, #MC2
MOV EPCR, A
MOV A, #baddr
MOV ADDR, A
MOV A, R0
MOV DATR, A
MOV A, R1
MOV DATR, A
MOV A, R2
MOV DATR, A
MOV A, R3
MOV DATR, A
RESULT
increment mode control word
select increment mode
EEPROM Latch 0 address
(AD0 = AD1 = 0)
send EEPROM Latch 0 address to
ADDR
load 1st byte from Register 0
send 1st byte to EEPROM Latch 0
load 2nd byte from Register 1
send 2nd byte to EEPROM Latch 1
load 3rd byte from Register 2
send 3rd byte to EEPROM Latch 2
load 4th byte from Register 3
send 4th byte to EEPROM Latch 3
7.5.2 READ BYTE
Since ADDR auto-increments after a read cycle regardless
of the page boundary, successive bytes can efficiently be
read by repeating the last instruction.
Table 20 Read byte
INSTRUCTION
RESULT
MOV A, #RDADDR load read address
MOV ADDR, A
send address to ADDR
MOV A, DATR
read EEPROM data
7.5.3 WRITE PAGE
The write cycle performs a logical OR between the data in
the EEPROM latches and that in the addressed EEPROM
page. To actually copy the data from the EEPROM
latches, the corresponding bytes in the page should
previously have been erased.
The EEPROM latches are preset as described in
Section 7.5.1. The actual transfer to the EEPROM is then
performed as shown in Table 21.
The last instruction also starts Timer 2. The data in the
EEPROM latches are ORed with that in the corresponding
page bytes within 5 ms. A single-byte write is simply a
special case of ‘write page’.
ADDR auto-increments after the write cycle. If AD0 and
AD1 addressed EEPROM Latch 3 prior to the write cycle,
ADDR will point to the next EEPROM page (by bits AD2
to AD6) and to EEPROM Latch 0 (by bits AD0 and AD1).
This allows efficient coding of multi-page write operations.
Table 21 Write page
INSTRUCTION
MOV A, #EWP + MC2
MOV EPCR, A
RESULT
‘write page’ control word
start ‘write page’ cycle
7.5.4 ERASE/WRITE PAGE
The EEPROM latches are preset as described in
Section 7.5.1. The page byte corresponding to the
asserted flags (among F0 to F3) are erased and re-written
with the contents of the respective EEPROM latches.
The last instruction also starts Timer 2. Erasure takes
5 ms upon which Timer Register T2 reloads for another
5 ms cycle for writing. The top cycles together take 10 ms.
A single-byte erase/write is simply a special event of
‘erase/write page’.
ADDR auto-increments after the write cycle. If AD0 and
AD1 addressed EEPROM latch 3 prior to the write cycle,
ADDR will point to the next EEPROM page (by AD2 to
AD6) and to EEPROM latch 0 (by AD0 and AD1).
This allows efficient coding of multi-page erase/write
operations.
Table 22 Erase/write page
INSTRUCTION
MOV A, #EWP + MC3
MOV EPCR, A
RESULT
‘erase/write page’ control word
start ‘erase/write page’ cycle
1998 May 11
16
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