PCF85133 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
PCF85133 Datasheet PDF : 53 Pages
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NXP Semiconductors
PCF85133
Universal LCD driver for low multiplex rates
the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the
provision for preparing display information in an alternative bank and to be able to switch
to it once it is assembled.
7.10.6 Input bank selector
The input bank selector loads display data into the display RAM in accordance with the
selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode
or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command (see
Table 15). The input bank selector functions independently to the output bank selector.
7.11 Blinking
The display blink capabilities of the PCF85133 are very versatile. The whole display can
blink at frequencies selected by the blink-select command (see Table 16). The blink
frequencies are fractions of the clock frequency. The ratios between the clock and blink
frequencies depend on the blink mode selected (see Table 10).
Table 10. Blink frequencies
Blink mode Operating mode ratio
off
-
1
-f--c--l--k-
768
2
--f--c---l-k---
1536
3
--f--c---l-k---
3072
Blink frequency with respect to fclk (typical)
fclk = 1.970 kHz
fclk = 2.640 kHz
blinking off
blinking off
2.5
3.5
1.3
1.7
0.6
0.9
Unit
Hz
Hz
Hz
Hz
An additional feature is for an arbitrary selection of LCD segments to blink. This applies to
the static and 1:2 multiplex drive modes and can be implemented without any
communication overheads. By means of the output bank selector, the displayed RAM
banks are exchanged with alternate RAM banks at the blink frequency. This mode can
also be specified by the blink-select command.
In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of
LCD segments can blink by selectively changing the display RAM data at fixed time
intervals.
If the entire display can blink at a frequency other than the typical blink frequency. This
can be effectively performed by resetting and setting the display enable bit E at the
required rate using the mode-set command (see Table 12).
7.12 Command decoder
The command decoder identifies command bytes that arrive on the I2C-bus. The
commands available to the PCF85133 are defined in Table 11.
PCF85133
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 4 July 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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